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These are all implemented using Verilog for my Logic Design Laboratory Class （邏輯設計實驗）, and I am using a Basys3 FPGA Board.

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michellenovenda/Logic-Design-Laboratory

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Final Project
Final Project
 
 
Lab 1 - ALU Designs
Lab 1 - ALU Designs
 
 
Lab 2 - Counter
Lab 2 - Counter
 
 
Lab 3 - Clock Divider and LED Controller
Lab 3 - Clock Divider and LED Controller
 
 
Lab 4 - BCD Counters
Lab 4 - BCD Counters
 
 
Lab 5 - The Fancy Mask Vending Machine
Lab 5 - The Fancy Mask Vending Machine
 
 
Lab 6 - Theme Park Monorail
Lab 6 - Theme Park Monorail
 
 
Lab 7 - Digital Photo Frame
Lab 7 - Digital Photo Frame
 
 
Lab 8 - Music Player
Lab 8 - Music Player
 
 
README.md
README.md
 
 

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Logic-Design-Laboratory

These are all implemented using Verilog for my Logic Design Laboratory Class （邏輯設計實驗）, using a Basys3 FPGA Board.
basys3 fpga-board

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These are all implemented using Verilog for my Logic Design Laboratory Class （邏輯設計實驗）, and I am using a Basys3 FPGA Board.

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fsm verilog basys3-fpga-board

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