wishbone: Convert to the wishbone_soc interfacing, for better interoperability

[galibert]

The main difference is that the wishbone-soc Arbiter is round-robin, while minerva's current is priority. Not sure if it matters. If it does, I'll try to enhance w-soc's.

[whitequark]

I think this needs a line in install_requires in setup.py... amaranth-soc didn't have a release yet, so probably something like amaranth-soc @ https://github.com/amaranth-lang/amaranth-soc.git

[jfng]

The main difference is that the wishbone-soc Arbiter is round-robin, while minerva's current is priority. Not sure if it matters. If it does, I'll try to enhance w-soc's.

Minerva uses a read-only D-cache, alongside a write buffer (to allow early retirement of store operations). When a load causes a D-cache miss, the write buffer must be emptied to commit ongoing store operations, before starting a cache refill. The data bus arbiter is responsible for this, with a priority-based round-robin policy.

The instruction bus arbiter does not require a priority-based policy, but I'd prefer to reuse the same implementation for convenience, unless the upstream one is significantly lighter.

Could you adapt this PR to keep Minerva's WishboneArbiter and update setup.py ? LGTM otherwise!