hardcaml.v0.14.2 (ocaml#18396)

packages/hardcaml/hardcaml.v0.14.2/opam

@@ -0,0 +1,35 @@
+opam-version: "2.0"
+maintainer: "[email protected]"
+authors: ["Jane Street Group, LLC <[email protected]>"]
+homepage: "https://github.com/janestreet/hardcaml"
+bug-reports: "https://github.com/janestreet/hardcaml/issues"
+dev-repo: "git+https://github.com/janestreet/hardcaml.git"
+doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml/index.html"
+license: "MIT"
+build: [
+  ["dune" "build" "-p" name "-j" jobs]
+]
+depends: [
+  "ocaml"            {>= "4.07.0"}
+  "base"             {>= "v0.14" & < "v0.15"}
+  "ppx_jane"         {>= "v0.14" & < "v0.15"}
+  "ppx_sexp_conv"    {>= "v0.14" & < "v0.15"}
+  "stdio"            {>= "v0.14" & < "v0.15"}
+  "topological_sort" {>= "v0.14" & < "v0.15"}
+  "dune"             {>= "2.0.0"}
+  "ppxlib"           {>= "0.18.0"}
+  "zarith"           {>= "1.5"}
+]
+available: arch != "arm32" & arch != "x86_32"
+synopsis: "RTL Hardware Design in OCaml"
+description: "
+Hardcaml is an embedded DSL for designing and simulating hardware in OCaml.
+Generic hardware designs are easily expressed using features such as higher
+order functions, lists, maps etc.  A built in simulator allows designs to
+be simulated within Hardcaml.  Designs are converted to either Verilog or
+VHDL to interact with standard back end tooling.
+"
+url {
+  src: "https://github.com/janestreet/hardcaml/archive/v0.14.2.tar.gz"
+  checksum: "md5=392c84bfcf1e9931f40bbbbb995f7b0a"
+}