Merge branch 'master' into JDK-8306116-CLDR44

make/test/JtregNativeHotspot.gmk

@@ -851,6 +851,7 @@ ifeq ($(call isTargetOs, linux), true)
   BUILD_TEST_exeinvoke_exeinvoke.c_OPTIMIZATION := NONE
   BUILD_HOTSPOT_JTREG_EXECUTABLES_LIBS_exeFPRegs := -ldl
   BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libAsyncGetCallTraceTest := -ldl
+  BUILD_HOTSPOT_JTREG_LIBRARIES_LDFLAGS_libfast-math := -ffast-math
 else
   BUILD_HOTSPOT_JTREG_EXCLUDE += libtest-rw.c libtest-rwx.c \
       exeinvoke.c exestack-gap.c exestack-tls.c libAsyncGetCallTraceTest.cpp

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp

@@ -175,68 +175,68 @@
                         Register tmp1, Register tmp2,
                         int encForm);
 
- void clear_array_v(Register base, Register cnt);
+  void clear_array_v(Register base, Register cnt);
 
- void byte_array_inflate_v(Register src, Register dst,
-                           Register len, Register tmp);
+  void byte_array_inflate_v(Register src, Register dst,
+                            Register len, Register tmp);
 
- void char_array_compress_v(Register src, Register dst,
+  void char_array_compress_v(Register src, Register dst,
                             Register len, Register result,
                             Register tmp);
 
- void encode_iso_array_v(Register src, Register dst,
-                         Register len, Register result,
-                         Register tmp, bool ascii);
+  void encode_iso_array_v(Register src, Register dst,
+                          Register len, Register result,
+                          Register tmp, bool ascii);
 
- void count_positives_v(Register ary, Register len,
+  void count_positives_v(Register ary, Register len,
                         Register result, Register tmp);
 
- void string_indexof_char_v(Register str1, Register cnt1,
+  void string_indexof_char_v(Register str1, Register cnt1,
                             Register ch, Register result,
                             Register tmp1, Register tmp2,
                             bool isL);
 
- void minmax_fp_v(VectorRegister dst,
+  void minmax_fp_v(VectorRegister dst,
                   VectorRegister src1, VectorRegister src2,
                   BasicType bt, bool is_min, int vector_length);
 
- void minmax_fp_masked_v(VectorRegister dst, VectorRegister src1, VectorRegister src2,
-                         VectorRegister vmask, VectorRegister tmp1, VectorRegister tmp2,
-                         BasicType bt, bool is_min, int vector_length);
+  void minmax_fp_masked_v(VectorRegister dst, VectorRegister src1, VectorRegister src2,
+                          VectorRegister vmask, VectorRegister tmp1, VectorRegister tmp2,
+                          BasicType bt, bool is_min, int vector_length);
 
- void reduce_minmax_fp_v(FloatRegister dst,
-                         FloatRegister src1, VectorRegister src2,
-                         VectorRegister tmp1, VectorRegister tmp2,
-                         bool is_double, bool is_min, int vector_length,
-                         VectorMask vm = Assembler::unmasked);
+  void reduce_minmax_fp_v(FloatRegister dst,
+                          FloatRegister src1, VectorRegister src2,
+                          VectorRegister tmp1, VectorRegister tmp2,
+                          bool is_double, bool is_min, int vector_length,
+                          VectorMask vm = Assembler::unmasked);
 
- void reduce_integral_v(Register dst, Register src1,
+  void reduce_integral_v(Register dst, Register src1,
                         VectorRegister src2, VectorRegister tmp,
                         int opc, BasicType bt, int vector_length,
                         VectorMask vm = Assembler::unmasked);
 
- void vsetvli_helper(BasicType bt, int vector_length, LMUL vlmul = Assembler::m1, Register tmp = t0);
+  void vsetvli_helper(BasicType bt, int vector_length, LMUL vlmul = Assembler::m1, Register tmp = t0);
 
- void compare_integral_v(VectorRegister dst, VectorRegister src1, VectorRegister src2, int cond,
-                         BasicType bt, int vector_length, VectorMask vm = Assembler::unmasked);
+  void compare_integral_v(VectorRegister dst, VectorRegister src1, VectorRegister src2, int cond,
+                          BasicType bt, int vector_length, VectorMask vm = Assembler::unmasked);
 
- void compare_fp_v(VectorRegister dst, VectorRegister src1, VectorRegister src2, int cond,
-                   BasicType bt, int vector_length, VectorMask vm = Assembler::unmasked);
+  void compare_fp_v(VectorRegister dst, VectorRegister src1, VectorRegister src2, int cond,
+                    BasicType bt, int vector_length, VectorMask vm = Assembler::unmasked);
 
- // In Matcher::scalable_predicate_reg_slots,
- // we assume each predicate register is one-eighth of the size of
- // scalable vector register, one mask bit per vector byte.
- void spill_vmask(VectorRegister v, int offset){
-   vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
-   add(t0, sp, offset);
-   vse8_v(v, t0);
- }
+  // In Matcher::scalable_predicate_reg_slots,
+  // we assume each predicate register is one-eighth of the size of
+  // scalable vector register, one mask bit per vector byte.
+  void spill_vmask(VectorRegister v, int offset){
+    vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
+    add(t0, sp, offset);
+    vse8_v(v, t0);
+  }
 
- void unspill_vmask(VectorRegister v, int offset){
-   vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
-   add(t0, sp, offset);
-   vle8_v(v, t0);
- }
+  void unspill_vmask(VectorRegister v, int offset){
+    vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
+    add(t0, sp, offset);
+    vle8_v(v, t0);
+  }
 
   void spill_copy_vmask_stack_to_stack(int src_offset, int dst_offset, int vector_length_in_bytes) {
     assert(vector_length_in_bytes % 4 == 0, "unexpected vector mask reg size");

src/hotspot/os/bsd/os_bsd.cpp

@@ -78,6 +78,7 @@
 # include <dlfcn.h>
 # include <errno.h>
 # include <fcntl.h>
+# include <fenv.h>
 # include <inttypes.h>
 # include <poll.h>
 # include <pthread.h>
@@ -975,6 +976,41 @@ bool os::dll_address_to_library_name(address addr, char* buf,
 // in case of error it checks if .dll/.so was built for the
 // same architecture as Hotspot is running on
 
+void *os::Bsd::dlopen_helper(const char *filename, int mode) {
+#ifndef IA32
+  // Save and restore the floating-point environment around dlopen().
+  // There are known cases where global library initialization sets
+  // FPU flags that affect computation accuracy, for example, enabling
+  // Flush-To-Zero and Denormals-Are-Zero. Do not let those libraries
+  // break Java arithmetic. Unfortunately, this might affect libraries
+  // that might depend on these FPU features for performance and/or
+  // numerical "accuracy", but we need to protect Java semantics first
+  // and foremost. See JDK-8295159.
+
+  // This workaround is ineffective on IA32 systems because the MXCSR
+  // register (which controls flush-to-zero mode) is not stored in the
+  // legacy fenv.
+
+  fenv_t default_fenv;
+  int rtn = fegetenv(&default_fenv);
+  assert(rtn == 0, "fegetenv must succeed");
+#endif // IA32
+
+  void * result= ::dlopen(filename, RTLD_LAZY);
+
+#ifndef IA32
+  if (result  != nullptr && ! IEEE_subnormal_handling_OK()) {
+    // We just dlopen()ed a library that mangled the floating-point
+    // flags. Silently fix things now.
+    int rtn = fesetenv(&default_fenv);
+    assert(rtn == 0, "fesetenv must succeed");
+    assert(IEEE_subnormal_handling_OK(), "fsetenv didn't work");
+  }
+#endif // IA32
+
+  return result;
+}
+
 #ifdef __APPLE__
 void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
 #ifdef STATIC_BUILD
@@ -984,7 +1020,7 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
 
   void* result;
   JFR_ONLY(NativeLibraryLoadEvent load_event(filename, &result);)
-  result = ::dlopen(filename, RTLD_LAZY);
+  result = os::Bsd::dlopen_helper(filename, RTLD_LAZY);
   if (result != nullptr) {
     Events::log_dll_message(nullptr, "Loaded shared library %s", filename);
     // Successful loading
@@ -1017,7 +1053,7 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
 
   void* result;
   JFR_ONLY(NativeLibraryLoadEvent load_event(filename, &result);)
-  result = ::dlopen(filename, RTLD_LAZY);
+  result = os::Bsd::dlopen_helper(filename, RTLD_LAZY);
   if (result != nullptr) {
     Events::log_dll_message(nullptr, "Loaded shared library %s", filename);
     // Successful loading

src/hotspot/os/bsd/os_bsd.hpp

@@ -70,6 +70,8 @@ class os::Bsd {
   // Real-time clock functions
   static void clock_init(void);
 
+  static void *dlopen_helper(const char *path, int mode);
+
   // Stack repair handling
 
   // none present

src/hotspot/os/linux/os_linux.cpp

@@ -95,6 +95,7 @@
 # include <signal.h>
 # include <endian.h>
 # include <errno.h>
+# include <fenv.h>
 # include <dlfcn.h>
 # include <stdio.h>
 # include <unistd.h>
@@ -1802,6 +1803,25 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
 }
 
 void * os::Linux::dlopen_helper(const char *filename, char *ebuf, int ebuflen) {
+#ifndef IA32
+  // Save and restore the floating-point environment around dlopen().
+  // There are known cases where global library initialization sets
+  // FPU flags that affect computation accuracy, for example, enabling
+  // Flush-To-Zero and Denormals-Are-Zero. Do not let those libraries
+  // break Java arithmetic. Unfortunately, this might affect libraries
+  // that might depend on these FPU features for performance and/or
+  // numerical "accuracy", but we need to protect Java semantics first
+  // and foremost. See JDK-8295159.
+
+  // This workaround is ineffective on IA32 systems because the MXCSR
+  // register (which controls flush-to-zero mode) is not stored in the
+  // legacy fenv.
+
+  fenv_t default_fenv;
+  int rtn = fegetenv(&default_fenv);
+  assert(rtn == 0, "fegetenv must succeed");
+#endif // IA32
+
   void* result;
   JFR_ONLY(NativeLibraryLoadEvent load_event(filename, &result);)
   result = ::dlopen(filename, RTLD_LAZY);
@@ -1820,6 +1840,16 @@ void * os::Linux::dlopen_helper(const char *filename, char *ebuf, int ebuflen) {
   } else {
     Events::log_dll_message(nullptr, "Loaded shared library %s", filename);
     log_info(os)("shared library load of %s was successful", filename);
+#ifndef IA32
+    // Quickly test to make sure subnormals are correctly handled.
+    if (! IEEE_subnormal_handling_OK()) {
+      // We just dlopen()ed a library that mangled the floating-point
+      // flags. Silently fix things now.
+      int rtn = fesetenv(&default_fenv);
+      assert(rtn == 0, "fesetenv must succeed");
+      assert(IEEE_subnormal_handling_OK(), "fsetenv didn't work");
+    }
+#endif // IA32
   }
   return result;
 }

src/hotspot/share/adlc/formssel.hpp

@@ -257,7 +257,7 @@ class InstructForm : public Form {
   void                set_cisc_reg_mask_name(const char *rm_name) { _cisc_reg_mask_name = rm_name; }
   // Output cisc-method prototypes and method bodies
   void                declare_cisc_version(ArchDesc &AD, FILE *fp_cpp);
-  bool                define_cisc_version (ArchDesc &AD, FILE *fp_cpp);
+  void                define_cisc_version(ArchDesc& AD, FILE* fp_cpp);
 
   bool                check_branch_variant(ArchDesc &AD, InstructForm *short_branch);
 
@@ -273,7 +273,7 @@ class InstructForm : public Form {
   bool                has_short_branch_form() { return _short_branch_form != nullptr; }
   // Output short branch prototypes and method bodies
   void                declare_short_branch_methods(FILE *fp_cpp);
-  bool                define_short_branch_methods(ArchDesc &AD, FILE *fp_cpp);
+  void                define_short_branch_methods(ArchDesc& AD, FILE* fp_cpp);
 
   uint                alignment() { return _alignment; }
   void                set_alignment(uint val) { _alignment = val; }

src/hotspot/share/adlc/output_c.cpp

@@ -3099,42 +3099,6 @@ void ArchDesc::define_oper_interface(FILE *fp, OperandForm &oper, FormDict &glob
   }
 }
 
-//
-// Construct the method to copy _idx, inputs and operands to new node.
-static void define_fill_new_machnode(bool used, FILE *fp_cpp) {
-  fprintf(fp_cpp, "\n");
-  fprintf(fp_cpp, "// Copy _idx, inputs and operands to new node\n");
-  fprintf(fp_cpp, "void MachNode::fill_new_machnode(MachNode* node) const {\n");
-  if( !used ) {
-    fprintf(fp_cpp, "  // This architecture does not have cisc or short branch instructions\n");
-    fprintf(fp_cpp, "  ShouldNotCallThis();\n");
-    fprintf(fp_cpp, "}\n");
-  } else {
-    // New node must use same node index for access through allocator's tables
-    fprintf(fp_cpp, "  // New node must use same node index\n");
-    fprintf(fp_cpp, "  node->set_idx( _idx );\n");
-    // Copy machine-independent inputs
-    fprintf(fp_cpp, "  // Copy machine-independent inputs\n");
-    fprintf(fp_cpp, "  for( uint j = 0; j < req(); j++ ) {\n");
-    fprintf(fp_cpp, "    node->add_req(in(j));\n");
-    fprintf(fp_cpp, "  }\n");
-    // Copy machine operands to new MachNode
-    fprintf(fp_cpp, "  // Copy my operands, except for cisc position\n");
-    fprintf(fp_cpp, "  int nopnds = num_opnds();\n");
-    fprintf(fp_cpp, "  assert( node->num_opnds() == (uint)nopnds, \"Must have same number of operands\");\n");
-    fprintf(fp_cpp, "  MachOper **to = node->_opnds;\n");
-    fprintf(fp_cpp, "  for( int i = 0; i < nopnds; i++ ) {\n");
-    fprintf(fp_cpp, "    if( i != cisc_operand() ) \n");
-    fprintf(fp_cpp, "      to[i] = _opnds[i]->clone();\n");
-    fprintf(fp_cpp, "  }\n");
-    fprintf(fp_cpp, "  // Do not increment node index counter, since node reuses my index\n");
-    fprintf(fp_cpp, "  Compile* C = Compile::current();\n");
-    fprintf(fp_cpp, "  C->set_unique(C->unique() - 1);\n");
-    fprintf(fp_cpp, "}\n");
-  }
-  fprintf(fp_cpp, "\n");
-}
-
 //------------------------------defineClasses----------------------------------
 // Define members of MachNode and MachOper classes based on
 // operand and instruction lists
@@ -3230,7 +3194,6 @@ void ArchDesc::defineClasses(FILE *fp) {
     defineOut_RegMask(_CPP_MISC_file._fp, instr->_ident, reg_mask(*instr));
   }
 
-  bool used = false;
   // Output the definitions for expand rules & peephole rules
   _instructions.reset();
   for( ; (instr = (InstructForm*)_instructions.iter()) != nullptr; ) {
@@ -3249,15 +3212,12 @@ void ArchDesc::defineClasses(FILE *fp) {
       definePeephole(_CPP_PEEPHOLE_file._fp, instr);
 
     // Output code to convert to the cisc version, if applicable
-    used |= instr->define_cisc_version(*this, fp);
+    instr->define_cisc_version(*this, fp);
 
     // Output code to convert to the short branch version, if applicable
-    used |= instr->define_short_branch_methods(*this, fp);
+    instr->define_short_branch_methods(*this, fp);
   }
 
-  // Construct the method called by cisc_version() to copy inputs and operands.
-  define_fill_new_machnode(used, fp);
-
   // Output the definitions for labels
   _instructions.reset();
   while( (instr = (InstructForm*)_instructions.iter()) != nullptr ) {
@@ -4074,7 +4034,7 @@ void InstructForm::declare_cisc_version(ArchDesc &AD, FILE *fp_hpp) {
 
 //---------------------------define_cisc_version-------------------------------
 // Build CISC version of this instruction
-bool InstructForm::define_cisc_version(ArchDesc &AD, FILE *fp_cpp) {
+void InstructForm::define_cisc_version(ArchDesc& AD, FILE* fp_cpp) {
   InstructForm *inst_cisc = this->cisc_spill_alternate();
   if( AD.can_cisc_spill() && (inst_cisc != nullptr) ) {
     const char   *name      = inst_cisc->_ident;
@@ -4120,9 +4080,7 @@ bool InstructForm::define_cisc_version(ArchDesc &AD, FILE *fp_cpp) {
     fprintf(fp_cpp, "  return node;\n");
     fprintf(fp_cpp, "}\n");
     fprintf(fp_cpp, "\n");
-    return true;
   }
-  return false;
 }
 
 //---------------------------declare_short_branch_methods----------------------
@@ -4135,7 +4093,7 @@ void InstructForm::declare_short_branch_methods(FILE *fp_hpp) {
 
 //---------------------------define_short_branch_methods-----------------------
 // Build definitions for short branch methods
-bool InstructForm::define_short_branch_methods(ArchDesc &AD, FILE *fp_cpp) {
+void InstructForm::define_short_branch_methods(ArchDesc& AD, FILE* fp_cpp) {
   if (has_short_branch_form()) {
     InstructForm *short_branch = short_branch_form();
     const char   *name         = short_branch->_ident;
@@ -4164,9 +4122,7 @@ bool InstructForm::define_short_branch_methods(ArchDesc &AD, FILE *fp_cpp) {
     fprintf(fp_cpp, "  return node;\n");
     fprintf(fp_cpp, "}\n");
     fprintf(fp_cpp,"\n");
-    return true;
   }
-  return false;
 }
 
 

src/hotspot/share/gc/g1/g1SurvRateGroup.hpp

@@ -86,6 +86,9 @@ class G1SurvRateGroup : public CHeapObj<mtGC> {
   double surv_rate_pred(G1Predictions const& predictor, uint age) const {
     assert(is_valid_age(age), "must be");
 
+    // _stats_arrays_length might not be in sync with _num_added_regions in Cleanup pause.
+    age = MIN2(age, _stats_arrays_length - 1);
+
     return predictor.predict_in_unit_interval(_surv_rate_predictors[age]);
   }