Fail to parse array values for generics in VHDL 2008

[rameloni]

Hi, I recently came across this problem.

I have a module which defines a generic of type unconstrained array:

entity my_entity is
    generic (
        ALLOWED_INPUT_ITEMS         : generic_positive_array
    );
    port (
        clk_i : in std_logic
    );
end;

Where generic_positive_array is:

type generic_positive_array is array(natural range <>) of positive;

When I try to analyze the entity I specify the generic through the argument -gALLOWED_INPUT_ITEMS=(1,2,3,4,8,6) nvc fails with this error message:

 Fatal: (init): failed to parse "(1,2,3,4,8,6)" as type GENERIC_POSITIVE_ARRAY for generic ALLOWED_INPUT_ITEMS

This is a functionality that some commercial simulators have, like riviera pro, and it would be great if nvc will be able to implement the same functionality!

[rameloni]

I am using version 1.19.3