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VHDL 2019 Initialization: Cannot correctly resolve type from generic package

Status: Open.

#1528 In nickg/nvc;

· tobibis opened on May 6, 2026

Create Own Signals With VHPI (Or Other API)

Status: Open.

#1523 In nickg/nvc;

· lemmuh opened on Apr 29, 2026

Verilog: parameter declarations don't accept functions

Status: Open.

#1518 In nickg/nvc;

· malles030 opened on Apr 25, 2026

Coverage reported too low (lower than with modelsim)

Status: Open.

#1517 In nickg/nvc;

· obruendl opened on Apr 24, 2026

Crash during elaboration when accessing elements of nested generic packages

Status: Open.

#1503 In nickg/nvc;

· ALVAROPING1 opened on Apr 15, 2026

WASM build

build

Status: Open.

#1502 In nickg/nvc;

· oscargus opened on Apr 15, 2026

VHDL-2019: Generic sum with different types performance and consistency issue

Status: Open.

#1492 In nickg/nvc;

· bpadalino opened on Apr 10, 2026

Potential performance improvements for DSP-centric designs using numeric_std

Status: Open.

#1481 In nickg/nvc;

· malles030 opened on Apr 7, 2026

Packages with Array Generic Types and internal indicies of ArrayType

Status: Open.

#1479 In nickg/nvc;

· JimLewis opened on Apr 6, 2026

Subtype of constrained subtype is not treated as constrained

Status: Open.

#1475 In nickg/nvc;

· darsor opened on Apr 1, 2026

Decreased NVC analysis and simulation speed between 1.19.1 and 1.19.3

Status: Open.

#1470 In nickg/nvc;

· Paebbels opened on Mar 30, 2026

Fail to parse array values for generics in VHDL 2008

Status: Open.

#1465 In nickg/nvc;

· rameloni opened on Mar 26, 2026