UART

Universal Asynchronous Receiver Transmitter with a LCD show tool Verilog implementation

Project design can be found on UART.docx

UART options: BaudRate: 9600/115200 bps Parity Check: 0/1 bit length character 7/8

Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
Check_Frame.v		Check_Frame.v
Control.v		Control.v
Delay_TX.v		Delay_TX.v
FIFO.v		FIFO.v
Frame_Gen.v		Frame_Gen.v
LCD_enable.v		LCD_enable.v
README.md		README.md
Receiver.v		Receiver.v
TX.v		TX.v
UART.docx		UART.docx
UART.v		UART.v
UART_TB.v		UART_TB.v
delay.v		delay.v
delay_control.v		delay_control.v
majority.v		majority.v
mem.v		mem.v
top.ucf		top.ucf

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