Pinned Loading

1. ReducedLUT ReducedLUT Public

   ReducedLUT: Table Decomposition with "Don't Care" Conditions [FPGA'25]

   C++ 35 1

2. MartaAndronic/NeuraLUT MartaAndronic/NeuraLUT Public

   NeuraLUT-Assemble

   Python 50 14

3. CascadeLUT CascadeLUT Public

   Forked from MartaAndronic/NeuraLUT

   CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs [FPL'26]

   Python

4. MAX MAX Public

   A parameterizable SystemVerilog module for finding the maximum value and its index from chunked input data.

   SystemVerilog

5. RL-Racetrack-Solver RL-Racetrack-Solver Public

   Python

6. CMATMUL CMATMUL Public

   A cache-based matrix multiplication kernel

   C++ 1