open-edge-platform · cheeyanglee · Dec 16, 2025 · Dec 10, 2025 · Dec 12, 2025 · Dec 12, 2025
@@ -1,5 +1,5 @@
 {
   "Signatures": {
-    "linux-6.12.55.tar.gz": "c8076132f818c0a22b7fe9a1184769406f0a62d0b93e4516d7f1a6d24f3791c3"
+    "linux-6.12.59.tar.gz": "93dfe627d321f016291054449a8e4bf9051de19687fbf1a6f584a2b79f8f5d2c"
   }
 }
@@ -13,14 +13,14 @@
 
 Summary:        Linux API header files
 Name:           kernel-headers
-Version:        6.12.55
-Release:        2%{?dist}
+Version:        6.12.59
+Release:        1%{?dist}
 License:        GPLv2
 Vendor:         Intel Corporation
 Distribution:   Edge Microvisor Toolkit
 Group:          System Environment/Kernel
 URL:            https://www.kernel.org/pub/linux/kernel
-Source0:        https://www.kernel.org/pub/linux/kernel/v6.x/linux-6.12.55.tar.gz
+Source0:        https://www.kernel.org/pub/linux/kernel/v6.x/linux-6.12.59.tar.gz
 # Historical name shipped by other distros
 Provides:       glibc-kernheaders = %{version}-%{release}
 BuildArch:      noarch
@@ -41,7 +41,7 @@ cross-glibc package.
 %endif
 
 %prep
-%setup -q -n linux-6.12.55
+%setup -q -n linux-6.12.59
 
 %build
 make mrproper
@@ -76,6 +76,9 @@ done
 %endif
 
 %changelog
+* Thu Dec 11 2025 Lishan Liu <[email protected]> - 6.12.59-1
+- Update kernel to 6.12.59
+
 * Thu Nov 27 2025 Lishan Liu <[email protected]> - 6.12.55-2
 - Update audio and virtio gpu kernel config
 

@@ -0,0 +1,59 @@
+From 4384532f29b08a758e951581980b6a1428c950f0 Mon Sep 17 00:00:00 2001
+From: Qiuxu Zhuo <[email protected]>
+Date: Wed, 6 Nov 2024 11:35:45 +0000
+Subject: [PATCH 1/6] EDAC/igen6: Initialize edac_op_state according to the
+ configuration data
+
+Currently, igen6_edac sets edac_op_state to EDAC_OPSTATE_NMI, while the
+driver also supports memory errors reported from Machine Check. Initialize
+edac_op_state to the correct value according to the configuration data
+that the driver probed.
+
+Signed-off-by: Qiuxu Zhuo <[email protected]>
+Signed-off-by: Tony Luck <[email protected]>
+Link: https://lore.kernel.org/all/[email protected]
+---
+ drivers/edac/igen6_edac.c | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c
+index 28a168cc569385..0524b83c8ab335 100644
+--- a/drivers/edac/igen6_edac.c
++++ b/drivers/edac/igen6_edac.c
+@@ -1389,6 +1389,15 @@ static void unregister_err_handler(void)
+ 	unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME);
+ }
+
++static void opstate_set(struct res_config *cfg)
++{
++	/* Set the mode according to the configuration data. */
++	if (cfg->machine_check)
++		edac_op_state = EDAC_OPSTATE_INT;
++	else
++		edac_op_state = EDAC_OPSTATE_NMI;
++}
++
+ static int igen6_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ {
+ 	u64 mchbar;
+@@ -1406,6 +1415,8 @@ static int igen6_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ 	if (rc)
+ 		goto fail;
+
++	opstate_set(res_cfg);
++
+ 	for (i = 0; i < res_cfg->num_imc; i++) {
+ 		rc = igen6_register_mci(i, mchbar, pdev);
+ 		if (rc)
+@@ -1489,8 +1500,6 @@ static int __init igen6_init(void)
+ 	if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
+ 		return -EBUSY;
+
+-	edac_op_state = EDAC_OPSTATE_NMI;
+-
+ 	rc = pci_register_driver(&igen6_driver);
+ 	if (rc)
+ 		return rc;
+-- 
+2.43.0
+
@@ -0,0 +1,39 @@
+From 1e5d5fbf3f18d0c4b534c431fa71c065ee048a63 Mon Sep 17 00:00:00 2001
+From: "Zawawi, Muhammad Zul Husni" <[email protected]>
+Date: Thu, 20 Nov 2025 15:27:35 +0800
+Subject: [PATCH] drm/i915: Do not advertise about CCS
+
+Do not advertise CCS is available for
+selected platforms (DG1,TGL,ADL-S/P)
+as CCS is not actually functional on those.
+
+Signed-off-by: Dongwon Kim <[email protected]>
+Signed-off-by: Zawawi, Muhammad Zul Husni <[email protected]>
+---
+ drivers/gpu/drm/i915/i915_query.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
+index 7c6669cc4c96..72201c8d9ecd 100644
+--- a/drivers/gpu/drm/i915/i915_query.c
++++ b/drivers/gpu/drm/i915/i915_query.c
+@@ -159,6 +159,16 @@ query_engine_info(struct drm_i915_private *i915,
+ 	info_ptr = &query_ptr->engines[0];
+
+ 	for_each_uabi_engine(engine, i915) {
++		/* Do not advertise CCS is available for selected platforms
++		 * as CCS is not actually functional on those.
++		 */
++		if ((INTEL_INFO(i915)->platform == INTEL_DG1 ||
++				INTEL_INFO(i915)->platform == INTEL_TIGERLAKE ||
++				INTEL_INFO(i915)->platform == INTEL_ALDERLAKE_S ||
++				INTEL_INFO(i915)->platform == INTEL_ALDERLAKE_P) &&
++				engine->uabi_class == I915_ENGINE_CLASS_COMPUTE)
++			continue;
++
+ 		info.engine.engine_class = engine->uabi_class;
+ 		info.engine.engine_instance = engine->uabi_instance;
+ 		info.flags = I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE;
+-- 
+2.43.0
+
@@ -0,0 +1,37 @@
+From 22bfa1d0a8bacb0b9a80e92f5e6920ff4204c7bc Mon Sep 17 00:00:00 2001
+From: "Mazlan, Hazwan Arif" <[email protected]>
+Date: Tue, 4 Nov 2025 13:22:44 +0800
+Subject: [PATCH] i915/gt: Upgrade GuC 70.44.1 => 70.49.4
+
+FW Upstream: https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
+FW Upstream commit: 20251021&id=20cf22e50252d63cfd0d06b5026c21b7a77ad821
+
+Signed-off-by: Mazlan, Hazwan Arif <[email protected]>
+---
+ drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+index 86afc6d175c48..5005b45f0dace 100644
+--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
++++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+@@ -88,12 +88,12 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
+  * security fixes, etc. to be enabled.
+  */
+ #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \
+-	fw_def(METEORLAKE,   0, guc_maj(mtl,  70, 44, 1)) \
+-	fw_def(DG2,          0, guc_maj(dg2,  70, 44, 1)) \
+-	fw_def(ALDERLAKE_P,  0, guc_maj(adlp, 70, 44, 1)) \
++	fw_def(METEORLAKE,   0, guc_maj(mtl,  70, 49, 4)) \
++	fw_def(DG2,          0, guc_maj(dg2,  70, 49, 4)) \
++	fw_def(ALDERLAKE_P,  0, guc_maj(adlp, 70, 49, 4)) \
+ 	fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 70, 1, 1)) \
+ 	fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 69, 0, 3)) \
+-	fw_def(ALDERLAKE_S,  0, guc_maj(tgl,  70, 44, 1)) \
++	fw_def(ALDERLAKE_S,  0, guc_maj(tgl,  70, 49, 4)) \
+ 	fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  70, 1, 1)) \
+ 	fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  69, 0, 3)) \
+ 	fw_def(DG1,          0, guc_maj(dg1,  70, 5, 1)) \
+-- 
+2.43.0
+
@@ -0,0 +1,93 @@
+From c008b6393fbc6d5b748162907dc84e260c7b1922 Mon Sep 17 00:00:00 2001
+From: Orange Kao <[email protected]>
+Date: Wed, 6 Nov 2024 11:35:46 +0000
+Subject: [PATCH 2/6] EDAC/igen6: Add polling support
+
+Some PCs with Intel N100 (with PCI device 8086:461c, DID_ADL_N_SKU4)
+experienced issues with error interrupts not working, even with the
+following configuration in the BIOS.
+
+    In-Band ECC Support: Enabled
+    In-Band ECC Operation Mode: 2 (make all requests protected and
+                                   ignore range checks)
+    IBECC Error Injection Control: Inject Correctable Error on insertion
+                                   counter
+    Error Injection Insertion Count: 251658240 (0xf000000)
+
+Add polling mode support for these machines to ensure that memory error
+events are handled.
+
+Signed-off-by: Orange Kao <[email protected]>
+Signed-off-by: Tony Luck <[email protected]>
+Reviewed-by: Qiuxu Zhuo <[email protected]>
+Link: https://lore.kernel.org/all/[email protected]
+---
+ drivers/edac/igen6_edac.c | 30 ++++++++++++++++++++++++++++--
+ 1 file changed, 28 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c
+index 0524b83c8ab335..da89cb0d4df42c 100644
+--- a/drivers/edac/igen6_edac.c
++++ b/drivers/edac/igen6_edac.c
+@@ -1209,6 +1209,20 @@ static int igen6_pci_setup(struct pci_dev *pdev, u64 *mchbar)
+ 	return -ENODEV;
+ }
+
++static void igen6_check(struct mem_ctl_info *mci)
++{
++	struct igen6_imc *imc = mci->pvt_info;
++	u64 ecclog;
++
++	/* errsts_clear() isn't NMI-safe. Delay it in the IRQ context */
++	ecclog = ecclog_read_and_clear(imc);
++	if (!ecclog)
++		return;
++
++	if (!ecclog_gen_pool_add(imc->mc, ecclog))
++		irq_work_queue(&ecclog_irq_work);
++}
++
+ static int igen6_register_mci(int mc, u64 mchbar, struct pci_dev *pdev)
+ {
+ 	struct edac_mc_layer layers[2];
+@@ -1250,6 +1264,8 @@ static int igen6_register_mci(int mc, u64 mchbar, struct pci_dev *pdev)
+ 	mci->edac_cap = EDAC_FLAG_SECDED;
+ 	mci->mod_name = EDAC_MOD_STR;
+ 	mci->dev_name = pci_name(pdev);
++	if (edac_op_state == EDAC_OPSTATE_POLL)
++		mci->edac_check = igen6_check;
+ 	mci->pvt_info = &igen6_pvt->imc[mc];
+
+ 	imc = mci->pvt_info;
+@@ -1389,8 +1405,18 @@ static void unregister_err_handler(void)
+ 	unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME);
+ }
+
+-static void opstate_set(struct res_config *cfg)
++static void opstate_set(struct res_config *cfg, const struct pci_device_id *ent)
+ {
++	/*
++	 * Quirk: Certain SoCs' error reporting interrupts don't work.
++	 *        Force polling mode for them to ensure that memory error
++	 *        events can be handled.
++	 */
++	if (ent->device == DID_ADL_N_SKU4) {
++		edac_op_state = EDAC_OPSTATE_POLL;
++		return;
++	}
++
+ 	/* Set the mode according to the configuration data. */
+ 	if (cfg->machine_check)
+ 		edac_op_state = EDAC_OPSTATE_INT;
+@@ -1415,7 +1441,7 @@ static int igen6_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ 	if (rc)
+ 		goto fail;
+
+-	opstate_set(res_cfg);
++	opstate_set(res_cfg, ent);
+
+ 	for (i = 0; i < res_cfg->num_imc; i++) {
+ 		rc = igen6_register_mci(i, mchbar, pdev);
+-- 
+2.43.0
+
@@ -0,0 +1,61 @@
+From 22e60a53039e0f951345db05219e78e18f3f0870 Mon Sep 17 00:00:00 2001
+From: Qiuxu Zhuo <[email protected]>
+Date: Wed, 12 Feb 2025 16:33:54 +0800
+Subject: [PATCH 3/6] EDAC/igen6: Fix the flood of invalid error reports
+
+The ECC_ERROR_LOG register of certain SoCs may contain the invalid value
+~0, which results in a flood of invalid error reports in polling mode.
+
+Fix the flood of invalid error reports by skipping the invalid ECC error
+log value ~0.
+
+Fixes: e14232afa944 ("EDAC/igen6: Add polling support")
+Reported-by: Ramses <[email protected]>
+Closes: https://lore.kernel.org/all/[email protected]/
+Tested-by: Ramses <[email protected]>
+Reported-by: John <[email protected]>
+Closes: https://lore.kernel.org/all/p5YcxOE6M3Ncxpn2-Ia_wCt61EM4LwIiN3LroQvT_-G2jMrFDSOW5k2A9D8UUzD2toGpQBN1eI0sL5dSKnkO8iteZegLoQEj-DwQaMhGx4A=@proton.me/
+Tested-by: John <[email protected]>
+Signed-off-by: Qiuxu Zhuo <[email protected]>
+Signed-off-by: Tony Luck <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ drivers/edac/igen6_edac.c | 21 +++++++++++++++------
+ 1 file changed, 15 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c
+index da89cb0d4df42c..4c54de702156a4 100644
+--- a/drivers/edac/igen6_edac.c
++++ b/drivers/edac/igen6_edac.c
+@@ -816,13 +816,22 @@ static u64 ecclog_read_and_clear(struct igen6_imc *imc)
+ {
+ 	u64 ecclog = readq(imc->window + ECC_ERROR_LOG_OFFSET);
+
+-	if (ecclog & (ECC_ERROR_LOG_CE | ECC_ERROR_LOG_UE)) {
+-		/* Clear CE/UE bits by writing 1s */
+-		writeq(ecclog, imc->window + ECC_ERROR_LOG_OFFSET);
+-		return ecclog;
+-	}
++	/*
++	 * Quirk: The ECC_ERROR_LOG register of certain SoCs may contain
++	 *        the invalid value ~0. This will result in a flood of invalid
++	 *        error reports in polling mode. Skip it.
++	 */
++	if (ecclog == ~0)
++		return 0;
+
+-	return 0;
++	/* Neither a CE nor a UE. Skip it.*/
++	if (!(ecclog & (ECC_ERROR_LOG_CE | ECC_ERROR_LOG_UE)))
++		return 0;
++
++	/* Clear CE/UE bits by writing 1s */
++	writeq(ecclog, imc->window + ECC_ERROR_LOG_OFFSET);
++
++	return ecclog;
+ }
+
+ static void errsts_clear(struct igen6_imc *imc)
+-- 
+2.43.0
+
@@ -23,11 +23,11 @@ Signed-off-by: Daniele Palmas <[email protected]>
  drivers/bus/mhi/host/pm.c       | 3 ++-
  2 files changed, 3 insertions(+), 2 deletions(-)
 
-diff --git a/drivers/bus/mhi/host/internal.h b/drivers/bus/mhi/host/internal.h
-index d057e877932e3..304870cb7611e 100644
+Index: b/drivers/bus/mhi/host/internal.h
+===================================================================
 --- a/drivers/bus/mhi/host/internal.h
 +++ b/drivers/bus/mhi/host/internal.h
-@@ -67,7 +67,7 @@ extern const char * const mhi_ee_str[MHI_EE_MAX];
+@@ -67,7 +67,7 @@ extern const char * const mhi_ee_str[MHI
 
  #define MHI_IN_PBL(ee) (ee == MHI_EE_PBL || ee == MHI_EE_PTHRU || \
  			ee == MHI_EE_EDL)
@@ -36,23 +36,20 @@ index d057e877932e3..304870cb7611e 100644
  #define MHI_FW_LOAD_CAPABLE(ee) (ee == MHI_EE_PBL || ee == MHI_EE_EDL)
  #define MHI_IN_MISSION_MODE(ee) (ee == MHI_EE_AMSS || ee == MHI_EE_WFW || \
  				 ee == MHI_EE_FP)
-diff --git a/drivers/bus/mhi/host/pm.c b/drivers/bus/mhi/host/pm.c
-index 11c0e751f2239..a69d21075e98a 100644
+Index: b/drivers/bus/mhi/host/pm.c
+===================================================================
 --- a/drivers/bus/mhi/host/pm.c
 +++ b/drivers/bus/mhi/host/pm.c
-@@ -1263,10 +1263,11 @@ int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
+@@ -1279,10 +1279,11 @@ int mhi_sync_power_up(struct mhi_control
  		mhi_cntrl->ready_timeout_ms : mhi_cntrl->timeout_ms;
  	wait_event_timeout(mhi_cntrl->state_event,
  			   MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
 +			   mhi_cntrl->ee == MHI_EE_SBL ||
- 			   MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
+ 			   MHI_PM_FATAL_ERROR(mhi_cntrl->pm_state),
  			   msecs_to_jiffies(timeout_ms));
 
 -	ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
 +	ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee) || mhi_cntrl->ee == MHI_EE_SBL) ? 0 : -ETIMEDOUT;
  	if (ret)
  		mhi_power_down(mhi_cntrl, false);
 
--- 
-2.25.1
-