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Update rvfi_tracer and cva6.py #2684

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Update rvfi_tracer and cva6.py #2684

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2a34fdf
RVFI Tracer : Update tracer to support interrupts
AyoubJalali Jan 3, 2025
a104722
Randomize sv_seed by default
AyoubJalali Jan 3, 2025
e99af42
Change pc64 to pc
AyoubJalali Jan 3, 2025
44c9817
Fixes
AyoubJalali Jan 3, 2025
4c3abfb
cva6.py : add the capability to create a log for sv_seed
AyoubJalali Jan 4, 2025
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25 changes: 18 additions & 7 deletions corev_apu/tb/rvfi_tracer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ module rvfi_tracer #(

logic [31:0] cycles;
// Generate the trace based on RVFI
logic [63:0] pc64;
logic [CVA6Cfg.XLEN-1:0] pc;
string cause;
logic[31:0] end_of_test_q;
logic[31:0] end_of_test_d;
Expand All @@ -74,19 +74,25 @@ module rvfi_tracer #(
always_ff @(posedge clk_i) begin
end_of_test_q <= (rst_ni && (end_of_test_d[0] == 1'b1)) ? end_of_test_d : 0;
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
pc64 = {{CVA6Cfg.XLEN-CVA6Cfg.VLEN{rvfi_i[i].pc_rdata[CVA6Cfg.VLEN-1]}}, rvfi_i[i].pc_rdata};
pc = {{CVA6Cfg.XLEN-CVA6Cfg.VLEN{rvfi_i[i].pc_rdata[CVA6Cfg.VLEN-1]}}, rvfi_i[i].pc_rdata};
// print the instruction information if the instruction is valid or a trap is taken
if (rvfi_i[i].valid) begin
// Instruction information
$fwrite(f, "core 0: 0x%h (0x%h) DASM(%h)\n",
pc64, rvfi_i[i].insn, rvfi_i[i].insn);
if (rvfi_i[i].intr[2]) begin
$fwrite(f, "core INTERRUPT 0: 0x%h (0x%h) DASM(%h)\n",
pc, rvfi_i[i].insn, rvfi_i[i].insn);
end
else begin
$fwrite(f, "core 0: 0x%h (0x%h) DASM(%h)\n",
pc, rvfi_i[i].insn, rvfi_i[i].insn);
end
// Destination register information
if (rvfi_i[i].insn[1:0] != 2'b11) begin
$fwrite(f, "%h 0x%h (0x%h)",
rvfi_i[i].mode, pc64, rvfi_i[i].insn[15:0]);
rvfi_i[i].mode, pc, rvfi_i[i].insn[15:0]);
end else begin
$fwrite(f, "%h 0x%h (0x%h)",
rvfi_i[i].mode, pc64, rvfi_i[i].insn);
rvfi_i[i].mode, pc, rvfi_i[i].insn);
end
// Decode instruction to know if destination register is FP register.
// Handle both uncompressed and compressed instructions.
Expand Down Expand Up @@ -129,8 +135,13 @@ module rvfi_tracer #(
32'h5: cause = "LD_ACCESS_FAULT";
32'h6: cause = "ST_ADDR_MISALIGNED";
32'h7: cause = "ST_ACCESS_FAULT";
32'hb: cause = "ENV_CALL_MMODE";
endcase;
$fwrite(f, "%s exception @ 0x%h\n", cause, pc64);
if (rvfi_i[i].insn[1:0] != 2'b11) begin
$fwrite(f, "%s exception @ 0x%h (0x%h)\n", cause, pc, rvfi_i[i].insn[15:0]);
end else begin
$fwrite(f, "%s exception @ 0x%h (0x%h)\n", cause, pc, rvfi_i[i].insn);
end
end
end
end
Expand Down
2 changes: 1 addition & 1 deletion verif/sim/cva6.py
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Expand Up @@ -775,7 +775,7 @@ def parse_args(cwd):
help="switch AXI agent mode: yes for Active, no for Passive")
parser.add_argument("--gen_sv_seed", type=int, default=0,
help="Run test N times with random seed")
parser.add_argument("--sv_seed", type=str, default="1",
parser.add_argument("--sv_seed", type=str, default=str(random.getrandbits(31)),
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If the seed is random, the CI tests will be executed with different seeds. This means the CI will not be deterministic. This can be a problem when executing Dhrystone or Coremark tests for instance for which we monitor cycle number.
Moreover some CI tests can have random behavior in relation to the seed. Debug can be more difficult.

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You can fix you're sv_seed using cva6.py option --sv_seed = n , by default sv_seed is always 1 and this limit finding bugs and use 100% of the UVM advantage (randomization), for now in CI all tests are running with only one sv_seed.

But we should store uvm seed in a specific file and store them in the artifacts

help="Run test with a specific seed")
parser.add_argument("--isa_extension", type=str, default="",
help="Choose additional z, s, x extensions")
Expand Down
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