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Fix partially #1181 #2686

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merged 3 commits into from
Jan 8, 2025
Merged

Fix partially #1181 #2686

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2fdad97
remove ifndef VERILATOR
JeanRochCoulon Jan 3, 2025
f0dcc37
Merge branch 'master' into VERILATOR
JeanRochCoulon Jan 7, 2025
d1ccbb0
Merge branch 'master' into VERILATOR
JeanRochCoulon Jan 7, 2025
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2 changes: 0 additions & 2 deletions core/cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1533,9 +1533,7 @@ module cva6
// Parameter Check
// -------------------
// pragma translate_off
`ifndef VERILATOR
initial config_pkg::check_cfg(CVA6Cfg);
`endif
// pragma translate_on

// -------------------
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2 changes: 0 additions & 2 deletions core/cva6_fifo_v3.sv
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Expand Up @@ -209,7 +209,6 @@ module cva6_fifo_v3 #(
end

// pragma translate_off
`ifndef VERILATOR
initial begin
assert (DEPTH > 0)
else $error("DEPTH must be greater than 0.");
Expand All @@ -222,7 +221,6 @@ module cva6_fifo_v3 #(
empty_read :
assert property (@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i))
else $fatal(1, "Trying to pop data although the FIFO is empty.");
`endif
// pragma translate_on

endmodule // fifo_v3
2 changes: 0 additions & 2 deletions core/cva6_mmu/cva6_tlb.sv
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Expand Up @@ -400,7 +400,6 @@ for (
//--------------

//pragma translate_off
`ifndef VERILATOR

initial begin : p_assertions
assert ((TLB_ENTRIES % 2 == 0) && (TLB_ENTRIES > 1))
Expand Down Expand Up @@ -435,7 +434,6 @@ for (
$stop();
end

`endif
//pragma translate_on

endmodule
8 changes: 0 additions & 8 deletions core/frontend/frontend.sv
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Expand Up @@ -575,12 +575,4 @@ module frontend
.fetch_entry_ready_i(fetch_entry_ready_i) // to back-end
);

// pragma translate_off
`ifndef VERILATOR
initial begin
assert (CVA6Cfg.FETCH_WIDTH == 32 || CVA6Cfg.FETCH_WIDTH == 64)
else $fatal(1, "[frontend] fetch width != not supported");
end
`endif
// pragma translate_on
endmodule
2 changes: 0 additions & 2 deletions core/frontend/instr_queue.sv
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Expand Up @@ -551,7 +551,6 @@ module instr_queue
end

// pragma translate_off
`ifndef VERILATOR
replay_address_fifo :
assert property (@(posedge clk_i) disable iff (!rst_ni) replay_o |-> !i_fifo_address.push_i)
else $fatal(1, "[instr_queue] Pushing address although replay asserted");
Expand All @@ -562,6 +561,5 @@ module instr_queue
$error("Output select should be one-hot encoded");
$stop();
end
`endif
// pragma translate_on
endmodule
4 changes: 2 additions & 2 deletions core/include/config_pkg.sv
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Expand Up @@ -369,7 +369,6 @@ package config_pkg;
/// sense for all parameters, here is the place to sanity check them.
function automatic void check_cfg(cva6_cfg_t Cfg);
// pragma translate_off
`ifndef VERILATOR
assert (Cfg.RASDepth > 0);
assert (Cfg.BTBEntries == 0 || (2 ** $clog2(Cfg.BTBEntries) == Cfg.BTBEntries));
assert (Cfg.BHTEntries == 0 || (2 ** $clog2(Cfg.BHTEntries) == Cfg.BHTEntries));
Expand All @@ -379,7 +378,8 @@ package config_pkg;
assert (Cfg.NrPMPEntries <= 64);
assert (!(Cfg.SuperscalarEn && Cfg.RVF));
assert (!(Cfg.SuperscalarEn && Cfg.RVZCMP));
`endif
assert (Cfg.FETCH_WIDTH == 32 || Cfg.FETCH_WIDTH == 64)
else $fatal(1, "[frontend] fetch width != not supported");
// pragma translate_on
endfunction

Expand Down
2 changes: 0 additions & 2 deletions core/load_unit.sv
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Expand Up @@ -546,7 +546,6 @@ module load_unit
///////////////////////////////////////////////////////

//pragma translate_off
`ifndef VERILATOR
initial
assert (CVA6Cfg.DcacheIdWidth >= REQ_ID_BITS)
else $fatal(1, "DcacheIdWidth parameter is not wide enough to encode pending loads");
Expand All @@ -563,7 +562,6 @@ module load_unit
assert property (@(posedge clk_i) disable iff (~rst_ni)
ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LB, ariane_pkg::LBU}) |-> ldbuf_wdata.address_offset < 8)
else $fatal(1, "invalid address offset used with {LB, LBU}");
`endif
//pragma translate_on

endmodule
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