feat: Trace Ingress Port #2800
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feat: Trace Ingress Port #2800
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dassheladiya
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zarubaf
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cathales
suggested changes
Mar 4, 2025
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Hello @dassheladiya and @MaxCThales
Here are some suggestions, especially to make this contribution compatible with CVA6 configuration.
MaxCThales
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Mar 5, 2025
Co-authored-by: Côme <[email protected]>
Co-authored-by: Côme <[email protected]>
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MaxCThales
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Mar 13, 2025
Co-authored-by: MaxCThales <[email protected]>
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core/cva6_rvfi_probes.sv
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| instr.tval = ex_commit_i.tval; | ||
| end else begin | ||
| instr.tval = '0; | ||
| end |
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Overview
Adds support for Trace Interface or Trace Ingress Port (TIP) on CVA6
TIP is Interface between a RISC-V hart and the trace encoder
It generates information about the instruction retired.
The implementation is compliant with the Efficient Trace for RISC-V standard Version 2.0.2(https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0.2/riscv-trace-spec-asciidoc.pdf), specifically:
Chapter 4.1: Instruction Trace Interface Requirements
Chapter 4.2: Instruction Trace Interface
The current implementation supports the following TIP signals: iretire, itype, cause, tval, priv, iaddr, and time. For Instruction Type (itype) encoding, it supports the following: Exception, Interrupt, Exception or interrupt return, Nontaken branch, Taken branch, Uninferable jump.
Changed
Added new files:
"core/cva6_te_connector/rtl/cva6_te_connector.sv"
"core/cva6_te_connector/rtl/fsm.sv"
"core/cva6_te_connector/rtl/itype_detector.sv"
"core/cva6_te_connector/include/connector_pkg.sv"
Changed files:
"core/cva6.sv"
"core/cva6_rvfi_probes.sv"
"core/include/rvfi_types.svh"
"corev_apu/tb/ariane_testharness.sv"
What I have been able to test so far:
Simulation: Executed C binaries and observed the waveform of TIP.
What I have not yet tested:
Did not perform any formal verification.