issue_stage: add register renaming#2805
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Hello Riccardo, Thank you for your pull request! To be able to run the subsequent CI jobs, including synthesis and other benchmarks, the expected performance needs to be updated here in your PR: cva6/.gitlab-ci/scripts/report_benchmark.py Lines 26 to 27 in 77911d3 Your new values are 37474 for cv32a60x and 30056 for cv32a60x (you can find them here: https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_cva6_2805.html) |
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Thanks, done! |
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@cathales is it possible to see the Spyglass detailed report to fix the CI failure? |
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There are 6 new warnings "[W362] Unequal length in arithmetic comparison operator" in |
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I see. So there is no way of knowing what triggers these warnings? Additionally, should I update the remaining performance reference numbers of the CI as well? |
| assign rs1_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].rs1) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( | ||
| fwd_i.sbe[fwd_i.wb[k].trans_id].op | ||
| )) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr( | ||
| assign rs1_fwd_req[i][k] = ((fwd_i.wb[k].trans_id == rd_clobber_gpr[issue_instr_i[i].rs1] && (!ariane_pkg::is_rs1_fpr( |
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Likely these comparisons? The other ones you changed/added are either with a genvar (unsized-ish) or a variant from the seemingly correct enumerated type.
And there are 6 of them.
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@JeanRochCoulon would it be possible to obtain a detailed spyglass report to understand where the new SpyGlass warnings arise? Thanks! |
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Co-authored-by: Riccardo Tedeschi <riccardo.tedeschi6@unibo.it>
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The SpyGlass warnings are now fixed! |
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👋 Hi there! This pull request seems inactive. Need more help or have updates? Feel free to let us know. If there are no updates within the next few days, we'll go ahead and close this PR. 😊 |
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This PR introduces a register renaming scheme to eliminate WAW hazards, as depicted below. Note that this change is not toggled by a parameter, rather it is a redesign of a portion of the issue logic.