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Clean Verilator warning about X-IF addition while keeping the RTL SEC-safe (#292)
* Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line * [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present * [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present * [rtl][xif][verilator] Clean warnings about enum-logic[] width mismatch on Verilator, while keeping the design logically equivalent. This is due to the cve2_decoder's rf_wdata_sel_o signal, which has its width dependent of the X-IF.
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rtl/cve2_decoder.sv

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -210,7 +210,7 @@ module cve2_decoder #(
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multdiv_operator_o = MD_OP_MULL;
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multdiv_signed_mode_o = 2'b00;
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213-
rf_wdata_sel_o = RF_WD_EX;
213+
rf_wdata_sel_o = $bits(rf_wdata_sel_o)'({RF_WD_EX});
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rf_we = 1'b0;
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rf_ren_a_o = 1'b0;
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rf_ren_b_o = 1'b0;
@@ -617,7 +617,7 @@ module cve2_decoder #(
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end else begin
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// instruction to read/modify CSR
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csr_access_o = 1'b1;
620-
rf_wdata_sel_o = RF_WD_CSR;
620+
rf_wdata_sel_o = $bits(rf_wdata_sel_o)'({RF_WD_CSR});
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rf_we = 1'b1;
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if (~instr[14]) begin
@@ -643,7 +643,7 @@ module cve2_decoder #(
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rf_ren_a_o = x_issue_resp_register_read_i[0];
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rf_ren_b_o = x_issue_resp_register_read_i[1];
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rf_we = x_issue_resp_writeback_i;
646-
rf_wdata_sel_o = RF_WD_COPROC;
646+
rf_wdata_sel_o = $bits(rf_wdata_sel_o)'({RF_WD_COPROC});
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end
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end

rtl/cve2_id_stage.sv

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -418,7 +418,7 @@ module cve2_id_stage #(
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// Register file write data mux
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always_comb begin : rf_wdata_id_mux
421-
unique case (rf_wdata_sel)
421+
unique case ($bits(rf_wd_sel_e)'({rf_wdata_sel}))
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RF_WD_EX: rf_wdata_id_o = result_ex_i;
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RF_WD_CSR: rf_wdata_id_o = csr_rdata_i;
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RF_WD_COPROC: rf_wdata_id_o = XInterface? x_result_i.data : result_ex_i;

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