Modification to the debug interface for the creation of an output halted status.

doc/02_user/integration.rst

@@ -63,6 +63,7 @@ Instantiation Template
 
       // Debug interface
       .debug_req_i            (),
+      .debug_halted_o         (),
       .dm_halt_addr_i         (),
       .dm_exception_addr_i    (),
       .crash_dump_o           (),

doc/03_reference/debug.rst

@@ -23,6 +23,8 @@ Interface
 +==================================+=====================+======================================================================================+
 | ``debug_req_i``                  | input               | Request to enter Debug Mode                                                          |
 +----------------------------------+---------------------+--------------------------------------------------------------------------------------+
+| ``debug_halted_o``               | output              | Asserted if core enters Debug Mode                                                   |
++----------------------------------+---------------------+--------------------------------------------------------------------------------------+
 | ``dm_halt_addr_i``               | input               | Address to jump to when entering Debug Mode (default 0x1A110800)                     |
 +----------------------------------+---------------------+--------------------------------------------------------------------------------------+
 | ``dm_exception_addr_i``          | input               | Address to jump to when an exception occurs while in Debug Mode (default 0x1A110808) |

dv/riscv_compliance/rtl/cve2_riscv_compliance.sv

@@ -167,6 +167,7 @@ module cve2_riscv_compliance (
       .scramble_req_o         (                       ),
 
       .debug_req_i            ('b0                    ),
+      .debug_halted_o         (                       ),
       .dm_halt_addr_i         (32'h00000000           ),
       .dm_exception_addr_i    (32'h00000000           ),
       .crash_dump_o           (                       ),

rtl/cve2_core.sv

@@ -62,6 +62,7 @@ module cve2_core import cve2_pkg::*; #(
 
   // Debug Interface
   input  logic                         debug_req_i,
+  output logic                         debug_halted_o,
   input  logic [31:0]                  dm_halt_addr_i,
   input  logic [31:0]                  dm_exception_addr_i,
   output crash_dump_t                  crash_dump_o,
@@ -611,6 +612,11 @@ module cve2_core import cve2_pkg::*; #(
   assign crash_dump_o.last_data_addr = lsu_addr_last;
   assign crash_dump_o.exception_addr = csr_mepc;
 
+  ///////////////////////
+  // Debug output      //
+  ///////////////////////
+
+  assign debug_halted_o = debug_mode;
 
   // Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included
   `ifdef INC_ASSERT

rtl/cve2_top.sv

@@ -57,6 +57,7 @@ module cve2_top import cve2_pkg::*; #(
 
   // Debug Interface
   input  logic                         debug_req_i,
+  output logic                         debug_halted_o,
   input  logic [31:0]                  dm_halt_addr_i,
   input  logic [31:0]                  dm_exception_addr_i,
   output crash_dump_t                  crash_dump_o,
@@ -194,6 +195,7 @@ module cve2_top import cve2_pkg::*; #(
     .irq_pending_o(irq_pending),
 
     .debug_req_i,
+    .debug_halted_o,
     .dm_halt_addr_i,
     .dm_exception_addr_i,
     .crash_dump_o,

rtl/cve2_top_tracing.sv

@@ -52,6 +52,7 @@ module cve2_top_tracing import cve2_pkg::*; #(
 
   // Debug Interface
   input  logic                         debug_req_i,
+  output logic                         debug_halted_o,
   input  logic [31:0]                  dm_halt_addr_i,
   input  logic [31:0]                  dm_exception_addr_i,
   output crash_dump_t                  crash_dump_o,
@@ -146,6 +147,7 @@ module cve2_top_tracing import cve2_pkg::*; #(
     .irq_nm_i,
 
     .debug_req_i,
+    .debug_halted_o,
     .dm_halt_addr_i,
     .dm_exception_addr_i,
     .crash_dump_o,