Docs update

CONTRIBUTING.md

@@ -19,7 +19,7 @@ document is recommended reading.
 1. From GitHub: [fork](https://help.github.com/articles/fork-a-repo/) the [cve2](https://github.com/openhwgroup/cve2) repository
 2. Clone repository: `git clone https://github.com/[your_github_username]/cve2`
 3. Create your feature branch: `git checkout -b <my_branch>.`<br> Please uniquify your branch name.  See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md)
-for a useful nominclature.
+for a useful nomenclature.
 4. Make your edits...
 5. Commit your changes: `git commit -m 'Add some feature' -s`
 6. Push feature branch: `git push origin <my_branch>`

README.md

@@ -7,7 +7,7 @@ The core will be made compatible with the OpenHW Group OBI protocol, it will use
 
 # CV32E20 RISC-V Core
 
-CV32E20 is a production-quality open source source 32-bit RISC-V CPU core written in
+CV32E20 is a production-quality open source 32-bit RISC-V CPU core written in
 SystemVerilog. The CPU core is heavily parametrizable and well-suited for
 embedded control applications. CV32E20 is being extensively verified and has
 seen multiple tape-outs. CV32E20 supports the Integer (I) or Embedded (E),
@@ -16,7 +16,7 @@ Integer Multiplication and Division (M), and Compressed (C) extensions.
 The block diagram below shows the *small* parametrization with a 2-stage
 pipeline.
 
-<p align="center"><img src="doc/03_reference/images/blockdiagram.svg" width="650"></p>
+<p align="center"><img src="doc/03_reference/images/blockdiagram.drawio.svg" width="650"></p>
 
 CV32E20 was initially developed as part of the [PULP platform](https://www.pulp-platform.org)
 under the name [&#34;Zero-riscy&#34;](https://doi.org/10.1109/PATMOS.2017.8106976), and has been
@@ -47,10 +47,12 @@ Only the person who actually performs the merge can add these labels (you need c
 
 ## Configuration
 
+<!-- TODO: This section and numbers need to be updated considering that the example code was removed -->
+
 CV32E20 offers several configuration parameters to meet the needs of various application scenarios.
 The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features.
 The table below indicates performance, area, and verification status for a few selected configurations.
-These are configurations on which lowRISC is focusing for performance evaluation and design verification (see [supported configs](cve2_configs.yaml)).
+These are configurations on which OpenHW is focusing for performance evaluation and design verification (see [supported configs](cve2_configs.yaml)).
 
 | Config                            | "micro" | "small"               |
 | --------------------------------- | ------- | --------------------- |
@@ -72,21 +74,21 @@ Notes:
   Green indicates that verification is close to complete.
   Amber indicates that some verification has been performed, but the configuration is still experimental.
   Red indicates a configuration with minimal/no verification.
-* v.1.0.0 of the RISC-V Bit-Manipulation Extension is supported as well as the remaining sub-extensions of draft v.0.93 of the bitmanip spec.
+<!-- * v.1.0.0 of the RISC-V Bit-Manipulation Extension is supported as well as the remaining sub-extensions of draft v.0.93 of the bitmanip spec.
   The latter is *not ratified* and there may be changes before ratification.
-  See [Standards Compliance](https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html) in the Ibex documentation for more information.
+  See [Standards Compliance](https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html) in the Ibex documentation for more information. -->
 
 ## Documentation (to be updated)
 
 The CVE2 documentation can be
 [read online at ReadTheDocs](https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/). It is also contained in
 the `doc` folder of this repository.
 
-## Examples
+<!-- ## Examples
 
 The CVE2 repository includes [Simple System](examples/simple_system/README.md).
 This is an intentionally simple integration of CV32E20 with a basic system that targets simulation.
-It is intended to provide an easy way to get bare metal binaries running on CV32E20 in simulation.
+It is intended to provide an easy way to get bare metal binaries running on CV32E20 in simulation. -->
 
 ## Contributing
 

doc/02_user/getting_started.rst

@@ -1,9 +1,9 @@
 .. _getting-started:
 
-Getting Started with Ibex
+Getting Started with CVE2
 =========================
 
-This page discusses initial steps and requirements to start using Ibex in your design.
+This page discusses initial steps and requirements to start using CVE2 in your design.
 
 Identification CSRs
 -------------------
@@ -12,7 +12,7 @@ The RISC-V Privileged Architecture specifies several read-only CSRs that identif
 These are ``mvendorid``, ``marchid`` and ``mimpid``.
 The fixed, read-only values for these CSRs are defined in :file:`rtl/cve2_pkg.sv`.
 Implementers should carefully consider appropriate values for these registers.
-Ibex, as an open source implementation, has an assigned architecture ID (``marchid``) of 0x23 (equivalent to 0d35).
+CVE2, as an open source implementation, has an assigned architecture ID (``marchid``) of 0x23 (equivalent to 0d35).
 (Allocations are specified in `marchid.md of the riscv-isa-manual repository <https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md>`_.)
 If significant changes are made to the micro-architecture a different architecture ID should be used.
 The vendor ID and implementation ID (``mvendorid`` and ``mimpid``). The vendor ID (mvendorid) is assigned the value 0x602 and the implementation ID (mimpid) is assigned the value 0x0.

doc/02_user/index.rst

@@ -1,8 +1,10 @@
-Ibex User Guide
+.. _cve2_user_guide:
+
+CVE2 User Guide
 ===============
 
-The Ibex User Guide provides all necessary information to use Ibex.
-It is aimed at hardware developers integrating Ibex into a design, and software developers writing software running on Ibex.
+The CVE2 User Guide provides all necessary information to use CVE2.
+It is aimed at hardware developers integrating CVE2 into a design, and software developers writing software running on CVE2.
 
 .. toctree::
    :maxdepth: 1

doc/02_user/integration.rst

@@ -14,12 +14,10 @@ Instantiation Template
 .. code-block:: verilog
 
   cve2_top #(
-      .MHPMCounterNum   ( 0                                ),
+      .MHPMCounterNum   ( 10                               ),
       .MHPMCounterWidth ( 40                               ),
       .RV32E            ( 0                                ),
-      .RV32M            ( cve2_pkg::RV32MFast              ),
-      .RndCnstLfsrSeed  ( cve2_pkg::RndCnstLfsrSeedDefault ),
-      .RndCnstLfsrPerm  ( cve2_pkg::RndCnstLfsrPermDefault )
+      .RV32M            ( cve2_pkg::RV32MFast              )
   ) u_top (
       // Clock and reset
       .clk_i                  (),
@@ -38,7 +36,6 @@ Instantiation Template
       .instr_rvalid_i         (),
       .instr_addr_o           (),
       .instr_rdata_i          (),
-      .instr_rdata_intg_i     (),
       .instr_err_i            (),
 
       // Data memory interface
@@ -51,9 +48,27 @@ Instantiation Template
       .data_wdata_o           (),
       .data_wdata_intg_o      (),
       .data_rdata_i           (),
-      .data_rdata_intg_i      (),
       .data_err_i             (),
 
+      // Core-V Extension Interface (CV-X-IF)
+      // Issue Interface
+      .x_issue_valid_o        (),
+      .x_issue_ready_i        (),
+      .x_issue_req_o          (),
+      .x_issue_resp_i         (),
+
+      // Register Interface
+      .x_register_o           (),
+
+      // Commit Interface
+      .x_commit_valid_o       (),
+      .x_commit_o             (),
+
+      // Result Interface     (),
+      .x_result_valid_i       (),
+      .x_result_ready_o       (),
+      .x_result_i             (),
+
       // Interrupt inputs
       .irq_software_i         (),
       .irq_timer_i            (),
@@ -95,13 +110,13 @@ Parameters
 |                              |                     |            | "cve2_pkg::RV32MSingleCycle": 1-2 cycle multiplier, iterative divider |
 +------------------------------+---------------------+------------+-----------------------------------------------------------------------+
 
-Any parameter marked *EXPERIMENTAL* when enabled is not verified to the same standard as the rest of the Ibex core.
+Any parameter marked *EXPERIMENTAL* when enabled is not verified to the same standard as the rest of the CVE2 core.
 
-Note that Ibex uses SystemVerilog enum parameters e.g. for ``RV32M``.
+Note that CVE2 uses SystemVerilog enum parameters e.g. for ``RV32M``.
 This is well supported by most tools but some care is needed when overriding these parameters at the top level:
 
 * Synopsys VCS does not support overriding enum and string parameters at the top level via command line.
-  As a workaround, SystemVerilog defines are used in Ibex top level files simulated with VCS.
+  As a workaround, SystemVerilog defines are used in CVE2 top level files simulated with VCS.
   These defines can be set via command line.
 
 * Yosys does not support overriding enum parameters at the top level by setting enum names.

doc/02_user/system_requirements.rst

@@ -1,31 +1,32 @@
 System and Tool Requirements
 ============================
 
-The Ibex CPU core is written in SystemVerilog.
-We try to achieve a balance between the used language features (as described in our `style guide <https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md>`_) and reasonably wide tool support.
+The CVE2 CPU core is written in SystemVerilog.
+We try to achieve a balance between the used language features (as described in lowRISC's `style guide <https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md>`_) and reasonably wide tool support.
 
-The following tools are known to work with the RTL code of Ibex.
-Please `file an issue <https://github.com/lowRISC/ibex/issues>`_ if you experience problems with any of the listed tools, or if you have successfully used a tool with Ibex which is not listed here.
+The following tools are known to work with the RTL code of CVE2.
+Please `file an issue <https://github.com/openhwgroup/cve2/issues>`_ if you experience problems with any of the listed tools, or if you have successfully used a tool with CVE2 which is not listed here.
 
+- Altair DSim
 - Synopsys Design Compiler
 - Xilinx Vivado, version |tool_requirements.vivado| and up.
 - Verilator, version |tool_requirements.verilator| and up.
 - Synopsys VCS, version at least |tool_requirements.vcs|.
 - Cadence Incisive/Xcelium
-- Mentor Questa
+- Siemens EDA Questa
 - Aldec Riviera Pro
 
 To run the UVM testbench a RTL simulator which supports SystemVerilog and UVM 1.2 is required.
 The `documentation of riscv-dv <https://github.com/google/riscv-dv#prerequisites>`_ contains a list of supported simulators.
 
-To compile code that runs on Ibex, you'll need a RISC-V toolchain.
+To compile code that runs on CVE2, you'll need a RISC-V toolchain.
 This isn't part of the core as such, but is necessary for verification.
 See the :doc:`Verification <../03_reference/verification>` section of the Reference Guide for more details about which toolchains the project currently uses for testing.
 
 Tools with known issues
 -----------------------
 
-Not all EDA tools have enough SystemVerilog support to be able to work with the Ibex code base.
+Not all EDA tools have enough SystemVerilog support to be able to work with the CVE2 code base.
 Users of such tools are encouraged to file issues with the vendor.
 As a workaround, tools like `sv2v <https://github.com/zachjs/sv2v>`_ can pre-process the source code to an older version of Verilog.