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    • aha

      Public
      Python
      850715Updated Nov 5, 2024Nov 5, 2024
    • garnet

      Public
      Next generation CGRA generator
      Python
      BSD 3-Clause "New" or "Revised" License
      11106812Updated Nov 5, 2024Nov 5, 2024
    • lake

      Public
      Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
      Python
      BSD 3-Clause "New" or "Revised" License
      21876Updated Nov 5, 2024Nov 5, 2024
    • Aha Tutorial
      SCSS
      0000Updated Nov 3, 2024Nov 3, 2024
    • canal

      Public
      Python
      1601Updated Oct 28, 2024Oct 28, 2024
    • C++
      Other
      1278300Updated Oct 16, 2024Oct 16, 2024
    • Python
      2000Updated Sep 5, 2024Sep 5, 2024
    • lassen

      Public
      The PE for the second generation CGRA (garnet).
      Python
      416245Updated Sep 4, 2024Sep 4, 2024
    • clockwork

      Public
      A polyhedral compiler for hardware accelerators
      C++
      12000Updated Jul 29, 2024Jul 29, 2024
    • AhaM3SoC

      Public
      SoC Based on ARM Cortex-M3
      Verilog
      Apache License 2.0
      102511Updated May 17, 2024May 17, 2024
    • 1000Updated Feb 1, 2024Feb 1, 2024
    • doc

      Public
      Papers, Posters, Presentations, Documentation...
      51800Updated Jan 9, 2024Jan 9, 2024
    • gemstone

      Public
      Python
      31023Updated Sep 5, 2023Sep 5, 2023
    • JavaScript
      1107Updated Mar 3, 2023Mar 3, 2023
    • SystemVerilog
      BSD 3-Clause "New" or "Revised" License
      0100Updated Oct 5, 2022Oct 5, 2022
    • JTAG/Python/M3 code for Amber demo
      0000Updated May 20, 2022May 20, 2022
    • pdq

      Public
      Python
      0013Updated Oct 26, 2021Oct 26, 2021
    • onyx

      Public
      Tcl
      BSD 3-Clause "New" or "Revised" License
      1300Updated Oct 10, 2021Oct 10, 2021
    • Documentation for the entire CGRAFlow
      21800Updated Sep 17, 2021Sep 17, 2021
    • amber-vde

      Public
      Tcl
      0100Updated Aug 23, 2020Aug 23, 2020
    • Design with Generated Clocks
      Tcl
      0000Updated May 20, 2020May 20, 2020
    • GarnetFlow

      Public archive
      Shell
      0225Updated Mar 11, 2020Mar 11, 2020
    • CGRAFlow

      Public
      Integration test for entire CGRA flow
      C++
      BSD 3-Clause "New" or "Revised" License
      212210Updated Jan 17, 2020Jan 17, 2020
    • Python
      1100Updated Oct 24, 2019Oct 24, 2019
    • chipyard

      Public
      Pre-release starter template for custom Chisel projects
      C
      Other
      648200Updated Oct 5, 2019Oct 5, 2019
    • The applications for the Stanford AHA CGRA
      C++
      2300Updated Jun 2, 2019Jun 2, 2019
    • delta

      Public
      Python
      0000Updated May 2, 2019May 2, 2019
    • CoreIR based mapping tool for CGRA
      C++
      BSD 3-Clause "New" or "Revised" License
      46151Updated Apr 25, 2019Apr 25, 2019
    • PowerDomainDesign

      Public archive
      Verilog
      4600Updated Apr 11, 2019Apr 11, 2019
    • Official Repo for keeping track of and defining all primitives.
      BSD 3-Clause "New" or "Revised" License
      0220Updated Jan 11, 2019Jan 11, 2019