Skip to content

@pulp-platform pulp-platform

Change the repository type filter

All

    Repositories list

    323 repositories

    • auteur

      Public
      The avant-garde tensor unit?
      SystemVerilog
      •
      Other
      •0•1•0•0•Updated Jun 9, 2026Jun 9, 2026

    • datamover

      Public
      SystemVerilog
      •
      Other
      •2•2•7•1•Updated Jun 9, 2026Jun 9, 2026

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •355•1.6k•54•20•Updated Jun 9, 2026Jun 9, 2026

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •61•375•27•8•Updated Jun 9, 2026Jun 9, 2026

    • gwaihir

      Public
      aka Lago-Mio
      C
      •
      Other
      •2•4•3•6•Updated Jun 9, 2026Jun 9, 2026

    • ManyRVData

      Public
      This is the repository for CachePool architecture for the ManyRVData project
      C
      •4•3•0•2•Updated Jun 8, 2026Jun 8, 2026

    • Insitu-Cache

      Public
      SystemVerilog
      •
      Other
      •2•5•0•1•Updated Jun 8, 2026Jun 8, 2026

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •45•159•5•7•Updated Jun 8, 2026Jun 8, 2026

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvector
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •186•524•101•11•Updated Jun 8, 2026Jun 8, 2026

    • magia-sdk

      Public
      C
      •11•6•7•7•Updated Jun 8, 2026Jun 8, 2026

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •34•114•5•3•Updated Jun 8, 2026Jun 8, 2026

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •63•306•24•4•Updated Jun 8, 2026Jun 8, 2026

    • clic

      Public
      RISC-V fast interrupt controller
      interruptrisc-vclic
      interruptrisc-vclic
      SystemVerilog
      •
      Apache License 2.0
      •5•35•7•4•Updated Jun 8, 2026Jun 8, 2026

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •957•23•2•0•Updated Jun 8, 2026Jun 8, 2026

    • cluster_peripherals

      Public
      SystemVerilog
      •
      Other
      •5•1•1•1•Updated Jun 8, 2026Jun 8, 2026

    • regression_tests

      Public
      C
      •20•10•3•3•Updated Jun 8, 2026Jun 8, 2026

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •39•52•7•4•Updated Jun 8, 2026Jun 8, 2026

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •200•756•25•7•Updated Jun 5, 2026Jun 5, 2026

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is a…
      casicfpga
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •33•127•16•7•Updated Jun 5, 2026Jun 5, 2026

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •20•16•5•3•Updated Jun 4, 2026Jun 4, 2026

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •372•9•0•3•Updated Jun 4, 2026Jun 4, 2026

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •25•35•4•7•Updated Jun 4, 2026Jun 4, 2026

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      •
      Apache License 2.0
      •7•19•16•1•Updated Jun 4, 2026Jun 4, 2026

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •13•20•3•10•Updated Jun 3, 2026Jun 3, 2026

    • opope

      Public
      High frequency pipelined outer product
      SystemVerilog
      •
      Other
      •0•0•0•0•Updated Jun 3, 2026Jun 3, 2026

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •52•215•10•11•Updated Jun 3, 2026Jun 3, 2026

    • llvm-project

      Public
      C++
      •17k•15•7•1•Updated Jun 3, 2026Jun 3, 2026

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •162•21•0•7•Updated Jun 2, 2026Jun 2, 2026

    • cluster_icache

      Public
      An instruction cache for processor clusters, originally developed for the snitch cluster.
      SystemVerilog
      •
      Other
      •7•5•1•8•Updated Jun 2, 2026Jun 2, 2026

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •109•135•17•7•Updated Jun 2, 2026Jun 2, 2026
    ProTip! When viewing an organization's repositories, you can use the props. filter to filter by custom property.