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Merged
merged 2 commits into from
Oct 10, 2024
Merged

Release_Sim_1.5.7 #416

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9fa2bbc
Release_Sim_1.5.7
AYYAZmayo Oct 9, 2024
f7039ec
EDA-3292,corrects illegal O_BUF instantiations
AYYAZmayo Oct 10, 2024
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2 changes: 1 addition & 1 deletion genesis3/FPGA_PRIMITIVES_MODELS
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Submodule FPGA_PRIMITIVES_MODELS updated 17 files
+106 −0 blackbox_models/cell_sim_blackbox.v
+17 −5 primitive_parser.py
+194 −0 sim_models/tb/DLY_SEL_DECODER_tb.v
+208 −0 sim_models/tb/DLY_VALUE_MUX_tb.v
+1,757 −156 sim_models/tb/FIFO36K_tb.v
+184 −0 sim_models/tb/MIPI_RX_tb.v
+154 −0 sim_models/tb/MIPI_TX_tb.v
+83 −0 sim_models/tb/SOC_FPGA_INTF_DMA_tb.v
+89 −0 sim_models/verilog/DLY_SEL_DCODER.v
+89 −0 sim_models/verilog/DLY_SEL_DECODER.v
+63 −0 sim_models/verilog/DLY_VALUE_MUX.v
+111 −45 sim_models/verilog/FIFO36K.v
+194 −0 tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v
+208 −0 tb/DLY_VALUE_MUX/DLY_VALUE_MUX_tb.v
+1,755 −156 tb/FIFO36K/FIFO36K_tb.v
+184 −0 tb/MIPI_RX/MIPI_RX_tb.v
+154 −0 tb/MIPI_TX/MIPI_TX_tb.v
2 changes: 1 addition & 1 deletion src/synth_rapidsilicon.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -7880,7 +7880,7 @@ void collect_clocks (RTLIL::Module* module,
// WARNING; we may need to handle case where 'keep' attribute is on
// the I_BUF/O_BUF so that we cannot remove them.
//
#if 0
#if 1
remove_io_buffers(top_module);

// Bypass the assigns by replacing LHs by RHS. Assigns will be
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