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os-fpga / yosys_verific_rs Public

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Bug/eda 3326/pll clk handling#818

Merged

NadeemYaseen merged 4 commits intomainos-fpga/yosys_verific_rs:mainfrom

bug/EDA-3326/pll_clk_handlingos-fpga/yosys_verific_rs:bug/EDA-3326/pll_clk_handlingCopy head branch name to clipboard

Nov 18, 2024

Conversation Commits4 (4)Checks Files changed

Merged

Bug/eda 3326/pll clk handling#818
NadeemYaseen merged 4 commits intomainfrom
bug/EDA-3326/pll_clk_handling

Commits

Commits on Nov 17, 2024

Stopping pass through LUT creation for PLL_CLK signal on output primitives
behzadmehmood
committed
Merge branch 'main' of https://github.com/os-fpga/yosys_verific_rs into bug/EDA-3326/pll_clk_handling
behzadmehmood
committed
Incremented patch version
behzadmehmood
committed

Commits on Nov 18, 2024

Incremented patch version
behzadmehmood
committed

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