Stack with Register File

Implementation of a stack using Verilog hardware definitions. The circuit diagram is available in the resources folder with progress reports.

Building the code

This command generated the VCD file for viewing on GTKWave.

iverilog stack4.v -o stack4 reg.v lib.v alu.v tb_stack4_el.v && vvp stack4

This command is to open GTKWave.

gtkwave tb_stack4.vcd

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
buildV1.0		buildV1.0
buildV1.1		buildV1.1
resources		resources
LICENSE		LICENSE
README.md		README.md
alu.v		alu.v
lib.v		lib.v
reg.v		reg.v
stack4.v		stack4.v
tb_stack4_el.v		tb_stack4_el.v