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feat: Add R-type instructions #7

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Feb 22, 2024
Merged

feat: Add R-type instructions #7

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43 changes: 35 additions & 8 deletions src/cpu.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -276,14 +276,41 @@ pub fn exec_sub(cpu: &mut CPU, instr: u32) {
- cpu.xregs.regs[rs2(instr) as usize] as i32)
as u32;
}
pub fn exec_sll(cpu: &mut CPU, instr: u32) {}
pub fn exec_slt(cpu: &mut CPU, instr: u32) {}
pub fn exec_sltu(cpu: &mut CPU, instr: u32) {}
pub fn exec_xor(cpu: &mut CPU, instr: u32) {}
pub fn exec_srl(cpu: &mut CPU, instr: u32) {}
pub fn exec_sra(cpu: &mut CPU, instr: u32) {}
pub fn exec_or(cpu: &mut CPU, instr: u32) {}
pub fn exec_and(cpu: &mut CPU, instr: u32) {}
pub fn exec_sll(cpu: &mut CPU, instr: u32) {
cpu.xregs.regs[rd(instr) as usize] = ((cpu.xregs.regs[rs1(instr) as usize] as i32)
<< cpu.xregs.regs[rs2(instr) as usize] as i32)
as u32;
}
pub fn exec_slt(cpu: &mut CPU, instr: u32) {
cpu.xregs.regs[rd(instr) as usize] = ((cpu.xregs.regs[rs1(instr) as usize] as i32)
< cpu.xregs.regs[rs2(instr) as usize] as i32)
as u32;
}
pub fn exec_sltu(cpu: &mut CPU, instr: u32) {
cpu.xregs.regs[rd(instr) as usize] =
(cpu.xregs.regs[rs1(instr) as usize] < cpu.xregs.regs[rs2(instr) as usize]) as u32;
}
pub fn exec_xor(cpu: &mut CPU, instr: u32) {
cpu.xregs.regs[rd(instr) as usize] =
cpu.xregs.regs[rs1(instr) as usize] ^ cpu.xregs.regs[rs2(instr) as usize];
}
pub fn exec_srl(cpu: &mut CPU, instr: u32) {
cpu.xregs.regs[rd(instr) as usize] =
cpu.xregs.regs[rs1(instr) as usize] >> cpu.xregs.regs[rs2(instr) as usize];
}
pub fn exec_sra(cpu: &mut CPU, instr: u32) {
cpu.xregs.regs[rd(instr) as usize] = ((cpu.xregs.regs[rs1(instr) as usize] as i32)
>> cpu.xregs.regs[rs2(instr) as usize] as i32)
as u32;
}
pub fn exec_or(cpu: &mut CPU, instr: u32) {
cpu.xregs.regs[rd(instr) as usize] =
cpu.xregs.regs[rs1(instr) as usize] | cpu.xregs.regs[rs2(instr) as usize];
}
pub fn exec_and(cpu: &mut CPU, instr: u32) {
cpu.xregs.regs[rd(instr) as usize] =
cpu.xregs.regs[rs1(instr) as usize] & cpu.xregs.regs[rs2(instr) as usize];
}
pub fn exec_fence(cpu: &mut CPU, instr: u32) {}
pub fn exec_fence_i(cpu: &mut CPU, instr: u32) {}
pub fn exec_ecall(cpu: &mut CPU, instr: u32) {}
Expand Down
122 changes: 105 additions & 17 deletions tests/cpu_test.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -459,24 +459,112 @@ mod tests {
// sub x31, x5, x6
let instr: u32 = helper::set_r_type_instruction(6, 5, SUB as u8, 31);
cpu::exec_sub(&mut cpu_test, instr);
assert_eq!(cpu_test.xregs.regs[31], 0xfffffffa); // 0xfffffffa is -6
assert_eq!(cpu_test.xregs.regs[31], -6 as i32 as u32);
}
#[test]
fn test_exec_sll() {
let mut cpu_test = cpu::CPU::new();

// set x5=-2
helper::set_register_val(&mut cpu_test, 5, -2);
// set x6=4
helper::set_register_val(&mut cpu_test, 6, 4);
// sll x31, x5, x6
let instr: u32 = helper::set_r_type_instruction(6, 5, SLL as u8, 31);
cpu::exec_sll(&mut cpu_test, instr);
assert_eq!(cpu_test.xregs.regs[31], -32 as i32 as u32);
}
#[test]
fn test_exec_slt() {
let mut cpu_test = cpu::CPU::new();

// set x5=-2
helper::set_register_val(&mut cpu_test, 5, -2);
// set x6=4
helper::set_register_val(&mut cpu_test, 6, 4);
// slt x31, x5, x6
let instr: u32 = helper::set_r_type_instruction(6, 5, SLT as u8, 31);
cpu::exec_slt(&mut cpu_test, instr);
assert_eq!(cpu_test.xregs.regs[31], 1 as i32 as u32);
}
#[test]
fn test_exec_sltu() {
let mut cpu_test = cpu::CPU::new();

// set x5=-2
helper::set_register_val(&mut cpu_test, 5, -2);
// set x6=4
helper::set_register_val(&mut cpu_test, 6, 4);
// sltu x31, x5, x6
let instr: u32 = helper::set_r_type_instruction(6, 5, SLTU as u8, 31);
cpu::exec_sltu(&mut cpu_test, instr);
assert_eq!(cpu_test.xregs.regs[31], 0 as i32 as u32);
}
#[test]
fn test_exec_xor() {
let mut cpu_test = cpu::CPU::new();

// set x5=-2
helper::set_register_val(&mut cpu_test, 5, -2);
// set x6=4
helper::set_register_val(&mut cpu_test, 6, 4);
// xor x31, x5, x6
let instr: u32 = helper::set_r_type_instruction(6, 5, XOR as u8, 31);
cpu::exec_xor(&mut cpu_test, instr);
assert_eq!(cpu_test.xregs.regs[31], -6 as i32 as u32);
}
#[test]
fn test_exec_srl() {
let mut cpu_test = cpu::CPU::new();

// set x5=-2
helper::set_register_val(&mut cpu_test, 5, -2);
// set x6=4
helper::set_register_val(&mut cpu_test, 6, 4);
// srl x31, x5, x6
let instr: u32 = helper::set_r_type_instruction(6, 5, SRL as u8, 31);
cpu::exec_srl(&mut cpu_test, instr);
assert_eq!(cpu_test.xregs.regs[31], 268435455);
}
#[test]
fn test_exec_sra() {
let mut cpu_test = cpu::CPU::new();

// set x5=-2
helper::set_register_val(&mut cpu_test, 5, -17);
// set x6=4
helper::set_register_val(&mut cpu_test, 6, 4);
// sra x31, x5, x6
let instr: u32 = helper::set_r_type_instruction(6, 5, SRA as u8, 31);
cpu::exec_sra(&mut cpu_test, instr);
assert_eq!(cpu_test.xregs.regs[31], -2 as i32 as u32);
}
#[test]
fn test_exec_or() {
let mut cpu_test = cpu::CPU::new();

// set x5=-2
helper::set_register_val(&mut cpu_test, 5, -2);
// set x6=4
helper::set_register_val(&mut cpu_test, 6, 4);
// or x31, x5, x6
let instr: u32 = helper::set_r_type_instruction(6, 5, OR as u8, 31);
cpu::exec_or(&mut cpu_test, instr);
assert_eq!(cpu_test.xregs.regs[31], -2 as i32 as u32);
}
#[test]
fn test_exec_and() {
let mut cpu_test = cpu::CPU::new();

// set x5=-2
helper::set_register_val(&mut cpu_test, 5, -2);
// set x6=4
helper::set_register_val(&mut cpu_test, 6, 4);
// and x31, x5, x6
let instr: u32 = helper::set_r_type_instruction(6, 5, AND as u8, 31);
cpu::exec_and(&mut cpu_test, instr);
assert_eq!(cpu_test.xregs.regs[31], 4);
}
// #[test]
// fn test_exec_sll() {}
// #[test]
// fn test_exec_slt() {}
// #[test]
// fn test_exec_sltu() {}
// #[test]
// fn test_exec_xor() {}
// #[test]
// fn test_exec_srl() {}
// #[test]
// fn test_exec_sra() {}
// #[test]
// fn test_exec_or() {}
// #[test]
// fn test_exec_and() {}
// #[test]
// fn test_exec_fence() {}
// #[test]
Expand Down
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