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Add RISCV64 RVV backend #1037
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Add RISCV64 RVV backend #1037
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92ecbea
autogen: Add support for RV64-backend to come
hanno-becker 5123465
Initial risc-v vector extension support (using standard vector intrin…
mjosaarinen 3162c69
Adjust CI to RV64 assembly backend
hanno-becker aa618c5
RV64: Autogenerate twiddles
mkannwischer 4ab0bce
RV64: Add bounds assertions
hanno-becker 3698c93
RV64: Minor style and renaming changes
hanno-becker b6355f1
Bench: Implement cycle counting based on direct PMU access
mjosaarinen 67a1217
RV64: Allow arbitrary vector length, fallback to C if unsupported
hanno-becker 9c93e94
RV64: Add CI tests for RV64 VLEN=128,256,512,1024
hanno-becker 5d086c4
RV64: Remove unnecesary reduction after NTT
hanno-becker 03baed6
RV64: Remove poly_{add,sub} from backend
hanno-becker f46a086
RV64: Remove unnecessary split/merge operation
hanno-becker 0f65791
RV64: Avoid carry-in during Montgomery reduction
hanno-becker 2567720
RV64: Use lazy reduction in invNTT
hanno-becker bde3535
RV64: Avoid repeated VLEN-evaluation in rejection sampling
hanno-becker e4e90ef
Fix typo in mlkem/src/sampling.c
hanno-becker 50d4992
RV64: Make cast from unsigned->signed int explicit in rej_uniform
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[//]: # (SPDX-License-Identifier: CC-BY-4.0) | ||
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# RISC-V Vector Extension Backend | ||
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This is an arithmetic backend for CPUs implementing the RISC-V Vector Extension. The backend is functional for all physical `VLEN`, but the NTT and inverse NTT are so far only implemented for VLEN=256, falling back to the default C implementations for other VLENs. | ||
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## Requirements | ||
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- RISC-V 64-bit architecture | ||
- Vector extension (RVV) version 1.0 | ||
- Standard "gc" extensions (integer and compressed instructions) |
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