Finish prjcombine-siliconblue

[wanda-phi]

• handle IOBs
  • IOB locations should be recovered and added to the Chip structure
  • IOB bits should be added to the TileDb
  • investigate using ExtraNode for this instead of the current structure?
• LATCH_GLOBAL_OUT bits need to be collected
• handle triple-strength IO
  • annoyingly, the Bond structure needs to be changed to a multimap or something
• handle I2C, I2C_FIFO, SPI hard IP (necessary to get iCE40LM4K to actually emit a database, since otherwise we can't RE left/right IO interconnect)
  • figure out how to get icecube to actually use dedicated IOs; this may involve fixing the binary with a hammer)
  • figure out how to actually recover the dedicated IO coords with icecube
  • add to the reversing pot
• handle IO_I3C
• handle *OSC
• handle PLL
• handle FILTER_50NS
  • is there a way to emit it standalone? failing that ...
  • extract BelPins
  • add to the reversing pot
• handle *_DRV
• handle iCE65 left IO special
  • is there a way to actually make it accept anything other than SB_LVCMOS and SB_LVDS_INPUT? is it all a lie?
• handle LEDD_IP, LEDDA_IP, IR_IP
• handle DSP
• handle SPRAM
• handle SMCCLK
  • is there a way to make icecube accept it? (if not, just inject the right stuff manually into the database, who cares)
• handle VPP_2V5_TO_1P8V
• scan carefully through icecube to make sure we're not missing any bits
• figure out intermittent failures at RAM colbuf bits
• validate we're not missing anything in the empty bitstream
• make the database export to happen in the right place; support multiple devices in database
  • make sure we support (or at least don't crash on) cut-down devices
• see if we can coerce icecube to be a little more eager with BRAM cascades
• figure out why inter-PLB LUT cascades aren't working
• split IO NEG_TRIGGER to separate inversion bits
• timing
  • hook up SDF parser
  • collect timing parameters from SDF
  • add Verilog or maybe VHDL netlist parser
  • verify routing against back-annotated netlist
• figure out the boot applet stuff
• figure out what the T04 IO glitch fix is about, anyway
• figure out why the SPEED stuff doesn't work on T04
• look for database cleanup and deduplication opportunities
• perform in-hardware testing
  • figure out what else needs to be hw-tested
  • obtain devboards (strong preference for ones with JTAG exposed; just make breakout boards if necessary)
    • iCE65L01
    • iCE65L04
    • iCE65P04
    • iCE65L08
    • iCE40P01 (LP1K / HX1K / LP640 / HX640)
    • iCE40P03 (LP384)
    • iCE40P08 (LP8K / HX8K / LP4K / HX4K)
    • iCE40R04 (LM4K)
    • iCE40T04 (Ultra, aka iCE5LP[124]K)
    • iCE40T01 (UltraLite, aka iCE40UL1K)
    • iCE40T05 (UltraPlus, aka iCE40UP5K)
  • make sure LUT0 cascade works (or doesn't)
  • make sure IO separate ICLK and OCLK inversion actually works
  • make and validate SB_MAC16 behavioral model
  • figure out how JTAG works