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[ARM64_DYNAREC] Remove bloated x87 comp code
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@ptitSeb
ptitSeb committed Jan 8, 2025
1 parent a5c4d01 commit b99893d
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Showing 15 changed files with 30 additions and 76 deletions.
2 changes: 1 addition & 1 deletion src/dynarec/arm64/dynarec_arm64_0f.c
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Expand Up @@ -511,7 +511,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
GETGX(v0, 0);
GETEXSS(s0, 0, 0);
FCMPS(v0, s0);
FCOMI(x1, x2, 0, v0, s0, 1); // disabled precise cmp
FCOMI(x1, x2);
break;
case 0x30:
INST_NAME("WRMSR");
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2 changes: 1 addition & 1 deletion src/dynarec/arm64/dynarec_arm64_660f.c
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Expand Up @@ -312,7 +312,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
GETGX(v0, 0);
GETEXSD(q0, 0, 0);
FCMPD(v0, q0);
FCOMI(x1, x2, 0, v0, q0, 0); //disable precise cmp
FCOMI(x1, x2);
break;

case 0x38: // SSSE3 opcodes
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2 changes: 1 addition & 1 deletion src/dynarec/arm64/dynarec_arm64_6664.c
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Expand Up @@ -68,7 +68,7 @@ uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
VLDR64_REG(v1, ed, x4);
}
FCMPD(v0, v1);
FCOMI(x1, x2, 0, v0, v1, 0); //disable precise cmp
FCOMI(x1, x2);
break;

case 0x6F:
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2 changes: 1 addition & 1 deletion src/dynarec/arm64/dynarec_arm64_67.c
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Expand Up @@ -216,7 +216,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
VLD32(s0, ed, fixedaddress);
}
FCMPS(v0, s0);
FCOMI(x1, x2, 0, v0, s0, 1); //disabled precise cmp
FCOMI(x1, x2);
break;
default:
DEFAULT;
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2 changes: 1 addition & 1 deletion src/dynarec/arm64/dynarec_arm64_avx_0f.c
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Expand Up @@ -290,7 +290,7 @@ uintptr_t dynarec64_AVX_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int
GETGX(v0, 0);
GETEXSS(s0, 0, 0);
FCMPS(v0, s0);
FCOMI(x1, x2, 0, v0, s0, 1); //disable precise cmp
FCOMI(x1, x2);
break;

case 0x50:
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2 changes: 1 addition & 1 deletion src/dynarec/arm64/dynarec_arm64_avx_66_0f.c
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Expand Up @@ -270,7 +270,7 @@ uintptr_t dynarec64_AVX_66_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip,
GETGX(v0, 0);
GETEXSD(q0, 0, 0);
FCMPD(v0, q0);
FCOMI(x1, x2, 0, v0, q0, 0); //disable precise cmp
FCOMI(x1, x2);
break;

case 0x50:
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8 changes: 4 additions & 4 deletions src/dynarec/arm64/dynarec_arm64_d8.c
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Expand Up @@ -90,7 +90,7 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
break;
case 0xD8:
case 0xD9:
Expand All @@ -108,7 +108,7 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;
case 0xE0:
Expand Down Expand Up @@ -222,7 +222,7 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
FCVT_D_S(s0, s0);
FCMPD(v1, s0);
}
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
break;
case 3:
INST_NAME("FCOMP ST0, float[ED]");
Expand All @@ -236,7 +236,7 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
FCVT_D_S(s0, s0);
FCMPD(v1, s0);
}
FCOM(x1, x2, x3, x4, v1, s0, ST_IS_F(0));
FCOM(x1, x2, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;
case 4:
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2 changes: 1 addition & 1 deletion src/dynarec/arm64/dynarec_arm64_d9.c
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Expand Up @@ -128,7 +128,7 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD_0(v1);
}
FCOM(x1, x2, x3, x4, 0, 0, ST_IS_F(0)); // same flags...
FCOM(x1, x2, x3); // same flags...
break;
case 0xE5:
INST_NAME("FXAM");
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6 changes: 3 additions & 3 deletions src/dynarec/arm64/dynarec_arm64_da.c
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Expand Up @@ -130,7 +130,7 @@ uintptr_t dynarec64_DA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;
Expand Down Expand Up @@ -169,7 +169,7 @@ uintptr_t dynarec64_DA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
SXTL_32(v2, v2); // i32 -> i64
SCVTFDD(v2, v2); // i64 -> double
FCMPD(v1, v2);
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
break;
case 3:
INST_NAME("FICOMP ST0, Ed");
Expand All @@ -180,7 +180,7 @@ uintptr_t dynarec64_DA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
SXTL_32(v2, v2); // i32 -> i64
SCVTFDD(v2, v2); // i64 -> double
FCMPD(v1, v2);
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;
case 4:
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4 changes: 2 additions & 2 deletions src/dynarec/arm64/dynarec_arm64_db.c
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Expand Up @@ -155,7 +155,7 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOMI(x1, x2, x4, v1, v2, ST_IS_F(0));
FCOMI(x1, x2);
break;
case 0xF0:
case 0xF1:
Expand All @@ -174,7 +174,7 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOMI(x1, x2, x4, v1, v2, ST_IS_F(0));
FCOMI(x1, x2);
break;

default:
Expand Down
8 changes: 4 additions & 4 deletions src/dynarec/arm64/dynarec_arm64_dc.c
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Expand Up @@ -88,7 +88,7 @@ uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
break;
case 0xD8:
case 0xD9:
Expand All @@ -106,7 +106,7 @@ uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;
case 0xE0:
Expand Down Expand Up @@ -205,7 +205,7 @@ uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
VLD64(v2, wback, fixedaddress);
FCMPD(v1, v2);
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
break;
case 3:
INST_NAME("FCOMP ST0, double[ED]");
Expand All @@ -214,7 +214,7 @@ uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
VLD64(v2, wback, fixedaddress);
FCMPD(v1, v2);
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;
case 4:
Expand Down
4 changes: 2 additions & 2 deletions src/dynarec/arm64/dynarec_arm64_dd.c
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Expand Up @@ -118,7 +118,7 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
break;
case 0xE8:
case 0xE9:
Expand All @@ -136,7 +136,7 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;

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8 changes: 4 additions & 4 deletions src/dynarec/arm64/dynarec_arm64_de.c
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Expand Up @@ -90,7 +90,7 @@ uintptr_t dynarec64_DE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;
case 0xD9:
Expand All @@ -102,7 +102,7 @@ uintptr_t dynarec64_DE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;
Expand Down Expand Up @@ -215,7 +215,7 @@ uintptr_t dynarec64_DE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
SXTL_32(v2, v2);
SCVTFDD(v2, v2);
FCMPD(v1, v2);
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
break;
case 3:
INST_NAME("FICOMP ST0, word[ED]");
Expand All @@ -227,7 +227,7 @@ uintptr_t dynarec64_DE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
SXTL_32(v2, v2);
SCVTFDD(v2, v2);
FCMPD(v1, v2);
FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
FCOM(x1, x2, x3);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;
case 4:
Expand Down
4 changes: 2 additions & 2 deletions src/dynarec/arm64/dynarec_arm64_df.c
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Expand Up @@ -109,7 +109,7 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOMI(x1, x2, x4, v1, v2, ST_IS_F(0));
FCOMI(x1, x2);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;
case 0xF0:
Expand All @@ -130,7 +130,7 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
} else {
FCMPD(v1, v2);
}
FCOMI(x1, x2, x4, v1, v2, ST_IS_F(0));
FCOMI(x1, x2);
X87_POP_OR_FAIL(dyn, ninst, x3);
break;

Expand Down
50 changes: 2 additions & 48 deletions src/dynarec/arm64/dynarec_arm64_helper.h
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Expand Up @@ -939,7 +939,7 @@
#endif

// Generate FCOM with s1 and s2 scratch regs (the VCMP is already done)
#define FCOM(s1, s2, s3, s4, v1, v2, is_f) \
#define FCOM(s1, s2, s3) \
LDRH_U12(s3, xEmu, offsetof(x64emu_t, sw)); /*offset is 8bits right?*/\
MOV32w(s1, 0b0100011100000000); \
BICw_REG(s3, s3, s1); \
Expand All @@ -949,34 +949,11 @@
CSELw(s1, s2, s1, cEQ); \
MOV32w(s2, 0b01000101); /* unordered */ \
CSELw(s1, s2, s1, cVS); \
if(v1||v2) { \
Bcond(cVS, 11*4); \
Bcond(cEQ, 10*4); \
if(is_f) { \
ORRw_mask(s4, xZR, 12, 10); /*+inf*/ \
FMOVwS(s2, v1); \
CMPSw_REG(s2, s4); \
Bcond(cEQ, 5*4); /* same */ \
FMOVwS(s2, v2); \
ORRw_mask(s4, s4, 1, 0); /*-inf*/ \
CMPSw_REG(s2, s4); \
} else { \
ORRx_mask(s4, xZR, 1, 12, 10); /*+inf*/ \
FMOVxD(s2, v1); \
CMPSx_REG(s2, s4); \
Bcond(cEQ, 5*4); /* same */ \
FMOVxD(s2, v2); \
ORRx_mask(s4, s4, 1, 1, 0); /*-inf*/ \
CMPSx_REG(s2, s4); \
} \
Bcond(cNE, 4+4); /* same */ \
MOVZw(s2, 0); \
} \
ORRw_REG_LSL(s3, s3, s1, 8); \
STRH_U12(s3, xEmu, offsetof(x64emu_t, sw))

// Generate FCOMI with s1 and s2 scratch regs (the VCMP is already done)
#define FCOMI(s1, s2, s4, v1, v2, is_f) \
#define FCOMI(s1, s2) \
IFX(X_OF|X_AF|X_SF|X_PEND) { \
MOV32w(s2, 0b100011010101); \
BICw_REG(xFlags, xFlags, s2); \
Expand All @@ -996,29 +973,6 @@
MOV32w(s2, 0b01000000); /* zero */ \
CSELw(s1, s2, s1, cEQ); \
/* greater than leave 0 */ \
if(s4) { \
Bcond(cVS, 11*4); \
Bcond(cEQ, 10*4); \
if(is_f) { \
ORRw_mask(s4, xZR, 12, 10); /*+inf*/ \
FMOVwS(s2, v1); \
CMPSw_REG(s2, s4); \
Bcond(cEQ, 5*4); /* same */ \
FMOVwS(s2, v2); \
ORRw_mask(s4, s4, 1, 0); /*-inf*/ \
CMPSw_REG(s2, s4); \
} else { \
ORRx_mask(s4, xZR, 1, 12, 10); /*+inf*/ \
FMOVxD(s2, v1); \
CMPSx_REG(s2, s4); \
Bcond(cEQ, 5*4); /* same */ \
FMOVxD(s2, v2); \
ORRx_mask(s4, s4, 1, 1, 0); /*-inf*/ \
CMPSx_REG(s2, s4); \
} \
Bcond(cNE, 4+4); /* same */ \
MOVZw(s1, 0); \
} \
ORRw_REG(xFlags, xFlags, s1); \
} \
SET_DFNONE(s1); \
Expand Down

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