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Add vCLIC support #55

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Add vCLIC support #55

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ea873e2
Add vCLIC support
ezelioli Jan 23, 2025
0ce9178
CI: update Cheshire integration branch
ezelioli Mar 20, 2025
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2 changes: 1 addition & 1 deletion .github/workflows/integration.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,6 @@ jobs:
ip-name: cva6
org: pulp-platform
repo: cheshire
base-ref: cva6/pulp-v2.0.0-alpha.1
base-ref: a85deb3c9c11772417c064dc767dcda084fe5d87
token: ${{ secrets.CHESHIRE_TOKEN }}
lifetime: 14
134 changes: 108 additions & 26 deletions core/csr_regfile.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,8 @@ module csr_regfile
input logic [1:0] irq_i,
// selective hardware vectoring bit - CLIC
input logic clic_irq_shv_i,
// interrupt request bit - CLIC
input logic clic_irq_req_i,
// inter processor interrupt -> connected to machine mode sw - SUBSYSTEM
input logic ipi_i,
// debug request in - ID_STAGE
Expand Down Expand Up @@ -156,6 +158,8 @@ module csr_regfile
// TO_BE_COMPLETED - CLIC_CTRL
output logic [7:0] sintthresh_o,
// TO_BE_COMPLETED - CLIC_CTRL
output logic [7:0] vsintthresh_o,
// TO_BE_COMPLETED - CLIC_CTRL
output logic clic_irq_ready_o,
// we are in single-step mode - COMMIT_STAGE
output logic single_step_o,
Expand Down Expand Up @@ -284,10 +288,12 @@ module csr_regfile
logic [CVA6Cfg.XLEN-1:0] htval_q, htval_d;

logic [CVA6Cfg.XLEN-1:0] vstvec_q, vstvec_d;
logic [CVA6Cfg.XLEN-1:0] vstvt_q, vstvt_d;
logic [CVA6Cfg.XLEN-1:0] vsscratch_q, vsscratch_d;
logic [CVA6Cfg.XLEN-1:0] vsepc_q, vsepc_d;
logic [CVA6Cfg.XLEN-1:0] vscause_q, vscause_d;
logic [CVA6Cfg.XLEN-1:0] vstval_q, vstval_d;
riscv::intthresh_rv_t vsintthresh_q, vsintthresh_d;

logic [CVA6Cfg.XLEN-1:0] dcache_q, dcache_d;
logic [CVA6Cfg.XLEN-1:0] icache_q, icache_d;
Expand Down Expand Up @@ -364,6 +370,12 @@ module csr_regfile
assign clic_irq_ready_o = 1'b0;
end

if (CVA6Cfg.RVVCLIC) begin : gen_clic_vsintthresh_signal
assign vsintthresh_o = vsintthresh_q.th;
end else begin : gen_dummy_clic_vsintthresh_signal
assign vsintthresh_o = '0;
end

always_comb begin : csr_read_process
// a read access exception can only occur if we attempt to read a CSR which does not exist
read_access_exception = 1'b0;
Expand Down Expand Up @@ -432,15 +444,19 @@ module csr_regfile
else read_access_exception = 1'b1;
riscv::CSR_VSIE:
if (CVA6Cfg.RVH)
csr_rdata = (mie_q & VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] & hideleg_q) >> 1;
csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 : ((mie_q & VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] & hideleg_q) >> 1);
else read_access_exception = 1'b1;
riscv::CSR_VSIP:
if (CVA6Cfg.RVH)
csr_rdata = (mip_q & VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] & hideleg_q) >> 1;
csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 : ((mip_q & VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] & hideleg_q) >> 1);
else read_access_exception = 1'b1;
riscv::CSR_VSTVEC:
if (CVA6Cfg.RVH) csr_rdata = vstvec_q;
else read_access_exception = 1'b1;
riscv::CSR_VSTVT:
if (CVA6Cfg.RVVCLIC)
csr_rdata = clic_mode_o ? {vstvt_q, 8'b0} : '0; // vstvt reads 0 in CLINT mode
else read_access_exception = 1'b1;
riscv::CSR_VSSCRATCH:
if (CVA6Cfg.RVH) csr_rdata = vsscratch_q;
else read_access_exception = 1'b1;
Expand All @@ -462,6 +478,10 @@ module csr_regfile
end else begin
read_access_exception = 1'b1;
end
riscv::CSR_VSINTTHRESH:
if (CVA6Cfg.RVVCLIC)
csr_rdata = clic_mode_o ? {{CVA6Cfg.XLEN - 8{1'b0}}, vsintthresh_q} : '0; // vsintthresh reads 0 in CLINT mode
else read_access_exception = 1'b1;
// supervisor registers
riscv::CSR_SSTATUS: begin
if (CVA6Cfg.RVS) csr_rdata = mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0];
Expand Down Expand Up @@ -554,13 +574,16 @@ module csr_regfile
if (CVA6Cfg.RVH) csr_rdata = hideleg_q;
else read_access_exception = 1'b1;
riscv::CSR_HIE:
if (CVA6Cfg.RVH) csr_rdata = mie_q & HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0];
if (CVA6Cfg.RVH)
csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? (mie_q & riscv::MIP_SGEIP) : (mie_q & HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]);
else read_access_exception = 1'b1;
riscv::CSR_HIP:
if (CVA6Cfg.RVH) csr_rdata = mip_q & HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0];
if (CVA6Cfg.RVH)
csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 : (mip_q & HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]);
else read_access_exception = 1'b1;
riscv::CSR_HVIP:
if (CVA6Cfg.RVH) csr_rdata = mip_q & VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0];
if (CVA6Cfg.RVH)
csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 : (mip_q & VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]);
else read_access_exception = 1'b1;
riscv::CSR_HCOUNTEREN:
if (CVA6Cfg.RVH) csr_rdata = hcounteren_q;
Expand All @@ -572,7 +595,7 @@ module csr_regfile
if (CVA6Cfg.RVH) csr_rdata = htinst_q;
else read_access_exception = 1'b1;
riscv::CSR_HGEIE:
if (CVA6Cfg.RVH) csr_rdata = '0;
if (CVA6Cfg.RVH) csr_rdata = {hgeie_q[CVA6Cfg.XLEN-1:1], 1'b0};
else read_access_exception = 1'b1;
riscv::CSR_HGEIP:
if (CVA6Cfg.RVH) csr_rdata = '0;
Expand Down Expand Up @@ -1101,6 +1124,11 @@ module csr_regfile
en_ld_st_g_translation_d = en_ld_st_g_translation_q;
end

if (CVA6Cfg.RVVCLIC) begin
vstvt_d = vstvt_q;
vsintthresh_d = vsintthresh_q;
end

if (CVA6Cfg.RVS) begin
sepc_d = sepc_q;
scause_d = scause_q;
Expand Down Expand Up @@ -1216,13 +1244,19 @@ module csr_regfile
end
end
riscv::CSR_VSIE:
if (CVA6Cfg.RVH) mie_d = (mie_q & ~hideleg_q) | ((csr_wdata << 1) & hideleg_q);
else update_access_exception = 1'b1;
if (CVA6Cfg.RVH) begin
// Writes are legal but ignored in CLIC mode
if (!(CVA6Cfg.RVVCLIC && clic_mode_o))
mie_d = (mie_q & ~hideleg_q) | ((csr_wdata << 1) & hideleg_q);
end else update_access_exception = 1'b1;
riscv::CSR_VSIP: begin
if (CVA6Cfg.RVH) begin
// only the virtual supervisor software interrupt is write-able, iff delegated
mask = CVA6Cfg.XLEN'(riscv::MIP_VSSIP) & hideleg_q;
mip_d = (mip_q & ~mask) | ((csr_wdata << 1) & mask);
// Writes are legal but ignored in CLIC mode
if (!(CVA6Cfg.RVVCLIC && clic_mode_o)) begin
// only the virtual supervisor software interrupt is write-able, iff delegated
mask = CVA6Cfg.XLEN'(riscv::MIP_VSSIP) & hideleg_q;
mip_d = (mip_q & ~mask) | ((csr_wdata << 1) & mask);
end
end else begin
update_access_exception = 1'b1;
end
Expand All @@ -1234,6 +1268,12 @@ module csr_regfile
update_access_exception = 1'b1;
end
end
riscv::CSR_VSTVT: begin
if (CVA6Cfg.RVVCLIC) begin
// Writes are legal but ignored in CLINT mode
if (clic_mode_o) vstvt_d = csr_wdata[CVA6Cfg.XLEN-1:8];
end else update_access_exception = 1'b1;
end
riscv::CSR_VSSCRATCH:
if (CVA6Cfg.RVH) vsscratch_d = csr_wdata;
else update_access_exception = 1'b1;
Expand Down Expand Up @@ -1267,6 +1307,12 @@ module csr_regfile
update_access_exception = 1'b1;
end
end
riscv::CSR_VSINTTHRESH: begin
if (CVA6Cfg.RVVCLIC) begin
// Writes are legal but ignored in CLINT mode
if (clic_mode_o) vsintthresh_d.th = csr_wdata[7:0];
end else update_access_exception = 1'b1;
end
// sstatus is a subset of mstatus - mask it accordingly
riscv::CSR_SSTATUS: begin
if (CVA6Cfg.RVS) begin
Expand Down Expand Up @@ -1420,16 +1466,20 @@ module csr_regfile
end
riscv::CSR_HIE: begin
if (CVA6Cfg.RVH) begin
mask = HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0];
// In CLIC mode only SGEIE bit is writable
mask = (CVA6Cfg.RVVCLIC && clic_mode_o) ? CVA6Cfg.XLEN'(riscv::MIP_SGEIP) : HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0];
mie_d = (mie_q & ~mask) | (csr_wdata & mask);
end else begin
update_access_exception = 1'b1;
end
end
riscv::CSR_HIP: begin
if (CVA6Cfg.RVH) begin
mask = CVA6Cfg.XLEN'(riscv::MIP_VSSIP);
mip_d = (mip_q & ~mask) | (csr_wdata & mask);
// Writes are legal but ignored in CLIC mode
if (!(CVA6Cfg.RVVCLIC && clic_mode_o)) begin
mask = CVA6Cfg.XLEN'(riscv::MIP_VSSIP);
mip_d = (mip_q & ~mask) | (csr_wdata & mask);
end
end else begin
update_access_exception = 1'b1;
end
Expand Down Expand Up @@ -1464,11 +1514,9 @@ module csr_regfile
end
end
//TODO Hyp: implement hgeie write
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I think the TODO can be removed

Suggested change
//TODO Hyp: implement hgeie write

riscv::CSR_HGEIE: begin
if (!CVA6Cfg.RVH) begin
update_access_exception = 1'b1;
end
end
riscv::CSR_HGEIE:
if (CVA6Cfg.RVH) hgeie_d = {csr_wdata[CVA6Cfg.XLEN-1:1], 1'b0};
else update_access_exception = 1'b1;
riscv::CSR_HGATP: begin
if (CVA6Cfg.RVH) begin
// intercept HGATP writes if in HS-Mode and TVM is enabled
Expand Down Expand Up @@ -2002,13 +2050,17 @@ module csr_regfile
if (CVA6Cfg.RVH) begin
if ((ex_i.cause[CVA6Cfg.XLEN-1] && hideleg_q[ex_i.cause[$clog2(
CVA6Cfg.XLEN
)-1:0]]) || (~ex_i.cause[CVA6Cfg.XLEN-1] && hedeleg_q[ex_i.cause[$clog2(
)-1:0]]) && ~clic_mode_o ||
(~ex_i.cause[CVA6Cfg.XLEN-1] && hedeleg_q[ex_i.cause[$clog2(
CVA6Cfg.XLEN
)-1:0]])) begin
// trap to VS only if it is the currently active mode
trap_to_v = v_q;
end
end
end else if (ex_i.cause[CVA6Cfg.XLEN-1] && clic_mode_o) begin
trap_to_priv_lvl = riscv::priv_lvl_t'(ex_i.cause[25:24]);
if (CVA6Cfg.RVVCLIC) trap_to_v = ex_i.cause[26];
end
end

Expand All @@ -2021,7 +2073,12 @@ module csr_regfile
// this can either be user or supervisor mode
vsstatus_d.spp = priv_lvl_q[0];
// set cause
vscause_d = ex_i.cause[CVA6Cfg.XLEN-1] ? {ex_i.cause[CVA6Cfg.XLEN-1:2], 2'b01} : ex_i.cause;
vscause_d = (~clic_mode_o && ex_i.cause[CVA6Cfg.XLEN-1]) ? {ex_i.cause[CVA6Cfg.XLEN-1:2], 2'b01} : ex_i.cause;
// update the current and previous interrupt level
if (CVA6Cfg.RVVCLIC && clic_mode_o && ex_i.cause[CVA6Cfg.XLEN-1]) begin
mintstatus_d.vsil = ex_i.cause[23:16];
vscause_d[23:16] = mintstatus_q.vsil;
end
// set epc
vsepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
// set vstval
Expand Down Expand Up @@ -2342,6 +2399,9 @@ module csr_regfile
vsstatus_d.spp = 1'b0;
// set spie to 1
vsstatus_d.spie = 1'b1;
// restore vsintstatus
if (CVA6Cfg.RVVCLIC && clic_mode_o && vscause_q[CVA6Cfg.XLEN-1])
mintstatus_d.vsil = vscause_q[23:16];
end
end

Expand Down Expand Up @@ -2421,6 +2481,8 @@ module csr_regfile
end
assign irq_ctrl_o.mideleg = (CVA6Cfg.RVS) ? mideleg_q : '0;
assign irq_ctrl_o.hideleg = (CVA6Cfg.RVH) ? hideleg_q : '0;
assign irq_ctrl_o.hgeie = (CVA6Cfg.RVH) ? hgeie_q : '0;
assign irq_ctrl_o.vgein = (CVA6Cfg.RVH) ? hstatus_q.vgein : '0;
assign irq_ctrl_o.global_enable = ~(CVA6Cfg.DebugEn & debug_mode_q)
// interrupts are enabled during single step or we are not stepping
// No need to check interrupts during single step if we don't support DEBUG mode
Expand Down Expand Up @@ -2575,7 +2637,7 @@ module csr_regfile
wfi_d = wfi_q;
// if there is any (enabled) interrupt pending un-stall the core
// also un-stall if we want to enter debug mode
if ((CVA6Cfg.DebugEn && debug_req_i) || (!clic_mode_o && (|(mip_q & mie_q) || irq_i[1])) || clic_irq_ready_o) begin
if ((CVA6Cfg.DebugEn && debug_req_i) || (!clic_mode_o && (|(mip_q & mie_q) || irq_i[1])) || (CVA6Cfg.RVSCLIC && clic_mode_o && clic_irq_req_i)) begin
wfi_d = 1'b0;
// or alternatively if there is no exception pending and we are not in debug mode wait here
// for the interrupt
Expand All @@ -2590,7 +2652,11 @@ module csr_regfile
// output user mode stvec
if (CVA6Cfg.RVS && trap_to_priv_lvl == riscv::PRIV_LVL_S) begin
if (CVA6Cfg.RVSCLIC && clic_mode_o && clic_irq_shv_i && ex_i.cause[CVA6Cfg.XLEN-1]) begin
trap_vector_base_o = {stvt_q[CVA6Cfg.VLEN-1:8], 8'b0};
if (CVA6Cfg.RVSCLIC && trap_to_v) begin
trap_vector_base_o = {vstvt_q[CVA6Cfg.VLEN-1:8], 8'b0};
end else begin
trap_vector_base_o = {stvt_q[CVA6Cfg.VLEN-1:8], 8'b0};
end
end else if (CVA6Cfg.RVH && trap_to_v) begin
trap_vector_base_o = {vstvec_q[CVA6Cfg.VLEN-1:2], 2'b0};
end else begin
Expand All @@ -2613,13 +2679,13 @@ module csr_regfile
// significant benefit, we conciously diverge from the spec here by jumping to
// trap_vector_base instead.
if (ex_i.cause[CVA6Cfg.XLEN-1] &&
((((CVA6Cfg.RVS || CVA6Cfg.RVU) && trap_to_priv_lvl == riscv::PRIV_LVL_M && (!CVA6Cfg.DirectVecOnly && mtvec_q[0])) || (!CVA6Cfg.RVS && !CVA6Cfg.RVU && (!CVA6Cfg.DirectVecOnly && mtvec_q[0])))
|| (CVA6Cfg.RVS && trap_to_priv_lvl == riscv::PRIV_LVL_S && !trap_to_v && stvec_q[0])
(((((CVA6Cfg.RVS || CVA6Cfg.RVU) && trap_to_priv_lvl == riscv::PRIV_LVL_M && (!CVA6Cfg.DirectVecOnly && mtvec_q[0])) || (!CVA6Cfg.RVS && !CVA6Cfg.RVU && (!CVA6Cfg.DirectVecOnly && mtvec_q[0]))) && ~clic_mode_o)
|| (CVA6Cfg.RVS && trap_to_priv_lvl == riscv::PRIV_LVL_S && !trap_to_v && stvec_q[0] && ~clic_mode_o)
|| (CVA6Cfg.RVSCLIC && clic_mode_o && clic_irq_shv_i))) begin
trap_vector_base_o[7:2] = ex_i.cause[5:0];
end
if (ex_i.cause[CVA6Cfg.XLEN-1] &&
(CVA6Cfg.RVH && trap_to_priv_lvl == riscv::PRIV_LVL_S && trap_to_v && vstvec_q[0])) begin
(CVA6Cfg.RVH && trap_to_priv_lvl == riscv::PRIV_LVL_S && trap_to_v && vstvec_q[0]) && ~clic_mode_o) begin
trap_vector_base_o[7:2] = {ex_i.cause[5:2], 2'b01};
end

Expand Down Expand Up @@ -2789,6 +2855,10 @@ module csr_regfile
sscratch_q <= {CVA6Cfg.XLEN{1'b0}};
stval_q <= {CVA6Cfg.XLEN{1'b0}};
satp_q <= {CVA6Cfg.XLEN{1'b0}};
if (CVA6Cfg.RVSCLIC) begin
stvt_q <= {CVA6Cfg.XLEN{1'b0}};
sintthresh_q <= 8'b0;
end
end

if (CVA6Cfg.RVH) begin
Expand All @@ -2812,6 +2882,10 @@ module csr_regfile
vstval_q <= {CVA6Cfg.XLEN{1'b0}};
vsatp_q <= {CVA6Cfg.XLEN{1'b0}};
en_ld_st_g_translation_q <= 1'b0;
if (CVA6Cfg.RVVCLIC) begin
vstvt_q <= {CVA6Cfg.XLEN{1'b0}};
vsintthresh_q <= 8'b0;
end
end
// timer and counters
cycle_q <= 64'b0;
Expand Down Expand Up @@ -2878,6 +2952,10 @@ module csr_regfile
sscratch_q <= sscratch_d;
if (CVA6Cfg.TvalEn) stval_q <= stval_d;
satp_q <= satp_d;
if (CVA6Cfg.RVSCLIC) begin
stvt_q <= stvt_d;
sintthresh_q <= sintthresh_d;
end
end
if (CVA6Cfg.RVH) begin
v_q <= v_d;
Expand All @@ -2901,6 +2979,10 @@ module csr_regfile
vstval_q <= vstval_d;
vsatp_q <= vsatp_d;
en_ld_st_g_translation_q <= en_ld_st_g_translation_d;
if (CVA6Cfg.RVVCLIC) begin
vstvt_q <= vstvt_d;
vsintthresh_q <= vsintthresh_d;
end
end
// timer and counters
cycle_q <= cycle_d;
Expand Down
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