Awesome LLM Circuit Agent

A curated list of papers, datasets, and resources related to Large Language Models (LLMs) for Circuit Design, covering both Digital (RTL) and Analog domains. This repository aims to track the rapid advancements in using AI agents for hardware design automation.

📖 Table of Contents

• Digital Circuit Design (RTL)
  • Code Generation & Synthesis
  • Verification & Testing
  • Optimization (PPA-aware)
  • Reinforcement Learning Approaches
  • Multi-Agent Systems & Workflows
  • Reasoning & Graph-Based
• Analog Circuit Design
  • Topology & Schematic Generation
  • Sizing & Optimization
  • Workflows & Multi-Agent
  • Specialized Applications
• Analog Mind Series (Behzad Razavi)
• Datasets & Benchmarks
• Resources & Learning
• Contributing

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💻 Digital Circuit Design (RTL)

📝 Code Generation & Synthesis

Title	Venue	Date	Code	Topic
Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation	arXiv	2026.04	-	Verilog Generation, Data-Efficient Fine-Tuning, Testbench Automation
Agent Factories for High Level Synthesis: How Far Can General-Purpose Coding Agents Go in Hardware Optimization?	arXiv	2026.03	-	HLS, Coding Agents, Multi-Agent, Hardware Optimization
IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution	arXiv	2026.03	-	Incremental RTL, Requirement Evolution, Traceability, EvoRTL-Bench
MING: An Automated CNN-to-Edge MLIR HLS framework	arXiv	2026.02	-	HLS, MLIR, CNN, Edge Computing
ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs	arXiv	2026.02	-	Agentic Context Evolution, RTL-Specialized LLM
AutoFSM: A Multi-agent Framework for FSM Code Generation with IR and SystemC-Based Testing	arXiv	2025.12	-	FSM, Multi-Agent, IR, SystemC
When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generation	arXiv	2025.12	-	LLM Unlearning, Hardware Code Generation
Mitigating Hallucinations and Omissions in LLMs for Invertible Problems: An Application to Hardware Logic Design Automation	arXiv	2025.12	-	Hallucination Mitigation, LCT, Autoencoder
PrefixGPT: Prefix Adder Optimization by a Generative Pre-trained Transformer	AAAI 2026	2025.11	Github	Prefix Adder, Transformer
QiMeng-CRUX: Narrowing the Gap between Natural Language and Verilog via Core Refined Understanding eXpression	arXiv	2025.11	-	NL2Verilog, CRUX
LocalV: Exploiting Information Locality for IP-level Verilog Generation	ICLR 2026	2025.09	-	Verilog, IP-level
SPARC-RTL: Stochastic Prompt-Assisted RTL Code Synthesis	ICLR 2026	2025.09	-	Prompt Engineering
VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts	arXiv	2025.10	-	Structure-Aware
DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation	arXiv	2025.10	Space	RAG
CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization	arXiv	2024.07	Model	Summarization
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework	DAC 2024	2024.03	-	Finetuning
VeriGen: A Large Language Model for Verilog Code Generation	arXiv	2023.07	Model	Finetuning
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design	arXiv	2023.05	Github	Conversational LLM, Tapeout
RTL-LLM: Large Language Models for Hardware Design	UC Berkeley	2025	-	Multi-Language

✅ Verification & Testing

Title	Venue	Date	Code	Topic
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs	arXiv	2026.04	-	SVA Generation, Hardware Verification, Task-Specific LLMs
Automated SVA Generation with LLMs	arXiv	2026.04	-	SVA Generation, Hardware Verification, LLMs
From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation	arXiv	2026.04	-	RTL Verification, Assertion Generation, Key Signal-Driven
UCAgent: An End-to-End Agent for Block-Level Functional Verification	arXiv	2026.03	-	Functional Verification, Block-Level, Multi-Stage Agent
QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis	arXiv	2026.03	-	Assertion Generation, NL2SVA, Data Synthesis
AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning	arXiv	2026.03	-	RTL Fixing, Concolic Testing, Functional Correctness
SpecLoop: An Agentic RTL-to-Specification Framework with Formal Verification Feedback Loop	arXiv	2026.03	-	RTL-to-Specification, Formal Verification, Agentic
FormalRTL: Verified RTL Synthesis at Scale	arXiv	2026.02	-	Verified RTL Synthesis, Formal Equivalence, Multi-Agent
GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation	arXiv	2026.01	-	Test Plan Generation, GRPO, RL
Duet: Agentic Design Understanding via Experimentation and Testing	arXiv	2025.12	-	Design Understanding, Experimentation, EDA Tools
R3A: Reliable RTL Repair Framework with Multi-Agent Fault Localization and Stochastic Tree-of-Thoughts Patch Generation	arXiv	2025.11	-	RTL Repair, Multi-Agent
TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation	arXiv	2025.11	-	Stimulus Gen, DPO
Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework	arXiv	2025.11	-	Neural-Symbolic
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT	arXiv	2025.11	-	Self-Verification
CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference	arXiv	2025.11	Github	HLS, RAG
BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis	arXiv	2025.06	-	Bug Synthesis, Multi-Agent
VeriSynth: Learning-Based Framework for Formal Verification of Hardware Designs	arXiv	2025.05	Github	Formal Verification
RTL-Repair: Fast Symbolic Repair of Hardware Design Code	ASPLOS 2024	2024.04	Github	RTL Repair, Symbolic

🚀 Optimization (PPA-aware)

Title	Venue	Date	Code	Topic
Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC	arXiv	2026.04	-	EDA Tools, Multi-Agent, Self-Evolution, ABC
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement	arXiv	2026.04	-	RTL Optimization, Agentic Workflow, Tool-Grounded Self-Improvement
POET: Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimization	arXiv	2026.03	-	PPA Optimization, Power-Oriented, Evolutionary Tuning
CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization	arXiv	2026.03	-	RTL Optimization, Multi-Agent, PPA
Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization	arXiv	2026.03	Github	QoR Optimization, Agentic Workflow, RAG
LUMINA: LLM-Guided GPU Architecture Exploration via Bottleneck Analysis	arXiv	2026.03	-	GPU DSE, Bottleneck Analysis, LLM-guided
TriGen: NPU Architecture for End-to-End Acceleration of Large Language Models based on SW-HW Co-Design	arXiv	2026.02	-	NPU Architecture, SW-HW Co-Design, LLM Acceleration
Automated QoR improvement in OpenROAD with coding agents	arXiv	2026.01	-	OpenROAD, Coding Agents, PPA, QoR
LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation	arXiv	2025.10	-	PPA Optimization
ChipSeek-R1: Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven RL	arXiv	2025.07	-	RL, PPA
ORFS-agent: Tool-Using Agents for Chip Design Optimization	arXiv	2025.06	Github	Physical Design
SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning	arXiv	2025.04	-	Symbolic Reasoning
Improving Large Language Model Hardware Generating Quality through Post-LLM Search	NeurIPS 2023	2023.12	-	Post-LLM Search

🤖 Reinforcement Learning Approaches

Title	Venue	Date	Code	Topic
RTLSeek: Boosting the LLM-Based RTL Generation with Diversity-Oriented RL	ICLR 2026	2025.09	-	Diversity-Oriented
EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation	arXiv	2025.11	-	Entropy-Aware
REvolution: An Evolutionary Framework for RTL Generation driven by LLMs	ASP-DAC 2026	2025.10	Github	Evolutionary Algo
VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning	arXiv	2025.08	Github	RL
VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog	ICLR 2026	2025.09	Github	RL, Reasoning
Improving LLM-Based Verilog Code Generation with Data Augmentation and RL	DATE 2025	2025.03	-	Data Augmentation
Large Language Model for Verilog Generation with Code-Structure-Guided RL	arXiv	2024.07	Code	Structure-Guided

🤝 Multi-Agent Systems & Workflows

Title	Venue	Date	Code	Topic
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs	arXiv	2026.04	-	Hierarchical RTL Generation, Multi-Agent, Large Hardware Designs
FluxEDA: A Unified Execution Infrastructure for Stateful Agentic EDA	arXiv	2026.03	-	Agentic EDA, Stateful Execution, Tool Integration
Exploring the Agentic Frontier of Verilog Code Generation	arXiv	2026.03	-	Agentic Verilog Generation, Tool-Using Agents, Empirical Evaluation
SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation	arXiv	2026.02	-	Multi-Agent, Distillation, Debug-Reasoning
ArchAgent: Agentic AI-driven Computer Architecture Discovery	arXiv	2026.02	-	Agentic AI, Architecture Discovery, Cache Replacement
Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation	arXiv	2026.01	-	Multi-Agent, Formal Verification, Contract-Aware
Architect in the Loop Agentic Hardware Design and Verification	arXiv	2025.12	Github	Agentic Design, Processor Design, Verification
David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?	arXiv	2025.12	-	Agentic AI, Small Models
CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systems	arXiv	2025.08	-	DSE, Multi-Agent
VFlow: Discovering Optimal Agentic Workflows for Verilog Generation	arXiv	2025.04	-	Agentic Workflow

🧠 Reasoning & Graph-Based

Title	Venue	Date	Code	Topic
Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL	arXiv	2026.03	-	Netlist Representation Learning, Data Augmentation
ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications	AAAI 2026	2025.12	-	RAG, Knowledge Graph, Reasoning
RTL++: Graph-enhanced LLM for RTL Code Generation	LAD '25	2025.05	-	Graph-enhanced
Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design	arXiv	2025.05	-	IR, Reasoning
CIRCUIT: A Benchmark for Circuit Interpretation and Reasoning Capabilities of LLMs	arXiv	2025.02	-	Reasoning
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model	arXiv	2025.04	Github	Hybrid Reasoning

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⚡ Analog Circuit Design

📐 Topology & Schematic Generation

Title	Venue	Date	Code	Topic
EEschematic: Multimodal-LLM Based AI Agent for Schematic Generation of Analog Circuit	arXiv	2025.10	Github	MLLM, Schematic
DiffCkt: A Diffusion Model-Based Hybrid Neural Network Framework for Automatic Transistor-Level Generation	arXiv	2025.07	-	Diffusion Model
SpiceMixer: Netlist-Level Circuit Evolution	arXiv	2025.06	-	Netlist Evolution
Schemato -- An LLM for Netlist-to-Schematic Conversion	arXiv	2024.11	-	Netlist-to-Schematic
LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits	arXiv	2024.07	-	Topology Generation

📏 Sizing & Optimization

Title	Venue	Date	Code	Topic
Self-Calibrating LLM-Based Analog Circuit Sizing with Interpretable Design Equations	arXiv	2026.04	-	Analog Sizing, Self-Calibration, Interpretable Design Equations
VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing	arXiv	2026.01	-	VLM, Collaborative Agent, Bayesian Optimization
HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization	arXiv	2025.11	-	Reasoning, Optimization
EEsizer: LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit	arXiv	2025.09	Github	Transistor Sizing
TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits	arXiv	2025.09	-	Topology-based
White-Box Reasoning: Synergizing LLM Strategy and gm/Id Data for Automated Analog Circuit Design	arXiv	2025.08	-	gm/Id, White-Box
RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization with Knowledge-infused RL	arXiv	2024.07	-	RL, Optimization
LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation	arXiv	2024.06	-	Bayesian Opt
Learning-driven Physically-aware Large-scale Circuit Gate Sizing	arXiv	2024.03	-	Gate Sizing

🔄 Workflows & Multi-Agent

Title	Venue	Date	Code	Topic
VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing	arXiv	2026.01	-	VLM, Collaborative Agent, Workflow
AnalogSAGE: Self-evolving Analog Design Multi-Agents with Stratified Memory and Grounded Experience	arXiv	2025.12	-	Multi-Agent, Self-evolving, Stratified Memory
AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing	arXiv	2025.11	-	Workflow
AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs	arXiv	2025.08	Github	MLLM, Unifying
A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction	arXiv	2025.06	-	Sizing Relationships
Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence	arXiv	2025.04	-	Multi-Agent

🔬 Specialized Applications

Title	Venue	Date	Code	Topic
Causal AI For AMS Circuit Design: Interpretable Parameter Effects Analysis	arXiv	2026.03	-	AMS, Causal Inference, Interpretability, SPICE
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation	arXiv	2025.07	-	Testbench Generation
LIMCA: LLM for Automating Analog In-Memory Computing Architecture Design Exploration	arXiv	2025.03	-	In-Memory Computing
FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design	arXiv	2025.05	-	Layout-Constrained
DocEDA: Automated Extraction and Design of Analog Circuits from Documents with Large Language Model	arXiv	2024.12	-	Document Extraction
AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design	arXiv	2024.07	-	Dataset, Benchmark
DE-HNN: An effective neural model for Circuit Netlist representation	arXiv	2024.04	-	Netlist Representation
Towards Understanding Fine-Tuning Mechanisms of LLMs via Circuit Analysis	arXiv	2025.02	-	Circuit Analysis

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📊 Datasets & Benchmarks

Title	Venue	Date	Code	Topic
HWE-Bench: Can Language Models Perform Board-level Schematic Designs?	arXiv	2026.03	-	Board-level Schematic Design, Benchmark, EDA Evaluation
Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes	arXiv	2026.03	-	RTL Evaluation, Synthesis-in-the-Loop, HQI
CktEvo: Repository-Level RTL Code Benchmark for Design Evolution	arXiv	2026.02	-	Repo-level RTL, Benchmark, PPA Evolution
VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation	arXiv	2026.02	-	Empirical Study, Prompt Engineering, Verilog Generation
ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design	arXiv	2026.01	-	Verilog Generation, Debugging, Reference Model
Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation	DATE 2026	2026.01	-	HLS, Benchmark, PPA Analysis
TuRTLe: A Unified Evaluation of LLMs for RTL Generation	MLCAD 2025	2025.04	Github	RTL Evaluation, Unified Benchmark
NotSoTiny: A Large, Living Benchmark for RTL Code Generation	arXiv	2025.12	Github	RTL Benchmark, Tiny Tapeout
VERIBENCH: End-to-End Formal Verification Benchmark for AI Code Generation in Lean 4	ICLR 2026	2025	-	Formal Verification
Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code	ICLR 2026	2025.09	-	Efficiency Benchmark
Refining Specs For LLM-Based RTL Agile Design	ICLR 2026	2025.09	-	Spec Refining
MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs	ASP-DAC 2025	2025.01	Github	Metric Reasoning
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model	ASP-DAC 2024	2024.01	Github	RTL Benchmark
VerilogEval: Evaluating Large Language Models for Verilog Code Generation	ICCAD 2023	2023.10	Github	Verilog Benchmark
ReasoningV-5K Dataset	HuggingFace	2025.04	Dataset	Reasoning Dataset
PyraNet-Verilog Dataset	HuggingFace	2024.07	Dataset	Verilog Dataset
Verilog_GitHub Dataset	HuggingFace	2023.07	Dataset	Verilog Dataset
VHDL GitHub Deduplicated	HuggingFace	2025	Dataset	VHDL Dataset
Chisel-Verilog Pairs	HuggingFace	2025	Dataset	Chisel Dataset
PyMTL-Verilog Pairs	HuggingFace	2025.05	Dataset	PyMTL Dataset

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🧠 Analog Mind Series (Behzad Razavi)

A series of articles by Prof. Behzad Razavi published in IEEE Solid-State Circuits Magazine (SSCM), exploring fundamental concepts and advanced topics in analog circuit design.

Title	Venue	Date	Link	Topic
Analog Mind (Part 1)	IEEE SSCM	2024.Q1	IEEE	Analog Design Fundamentals
Analog Mind (Part 2)	IEEE SSCM	2024.Q2	IEEE	Analog Design Concepts
Analog Mind (Part 3)	IEEE SSCM	2024.Q3	PDF	Advanced Analog Topics
Analog Mind (Part 4)	IEEE SSCM	2025.Q1	PDF	Advanced Analog Topics
Analog Mind (Part 5)	IEEE SSCM	2024.Q4	IEEE	Analog Design Insights
Analog Mind (Part 6)	IEEE SSCM	2025.Q1	IEEE	Analog Design Insights
Analog Mind (Part 7)	IEEE SSCM	2025.Q2	IEEE	Analog Design Insights
Analog Mind (Part 8)	IEEE SSCM	2025.Q3	IEEE	Analog Design Insights

For complete list of Analog Mind articles, see Behzad Razavi's IEEE Author Page

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📚 Resources & Learning

Title	Type	Topic
Energy Efficient Software Hardware CoDesign for Machine Learning: From TinyML to Large Language Models	Survey	Energy Efficiency, SW-HW Co-Design, ML Systems
SCALE-Sim TPU: Validating and Extending SCALE-Sim for TPUs	Paper	TPU, Cycle-Accurate Simulation, ML Compiler
AI+HW 2035: Shaping the Next Decade	Vision Paper	AI+HW Co-Design
ChatNeuroSim: An LLM Agent Framework for Automated Compute-in-Memory Accelerator Deployment and Optimization	Paper	CIM Accelerator, Agentic Optimization
BrainWave NPU Microarchitecture Analysis	Docs	NPU Architecture
EEschematic Presentation	Slides	AMS Circuit
ASIC Technology Lecture	Course	ASIC
Digital System Design PDF	PDF	Digital Design
Springer Book: Digital System Design	Book	Digital Design

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🤝 Contributing

We welcome contributions! If you know of a paper, tool, or resource that should be included, please:

1. Fork this repository
2. Add your entry following the existing format
3. Submit a pull request with a brief description

Contribution Guidelines

• Ensure the paper/resource is relevant to LLM-based circuit design (RTL/Analog) or hardware automation
• Include proper citation with title, venue, date, and links
• Add appropriate topic tags
• Maintain chronological order (newest first)
• Check for duplicates before submitting

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📄 Citation

If you find this repository useful for your research, please consider citing:

@misc{awesome-llm-circuit-agent,
  author = {Haiyan Qin},
  title = {Awesome LLM Circuit Agent: A Curated Collection of LLM-Driven Circuit Design Research},
  year = {2025},
  publisher = {GitHub},
  url = {https://github.com/qhy991/Awesome-LLM-Circuit-Agent}
}

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📜 License

This work is licensed under a Creative Commons Zero v1.0 Universal license.

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Last Updated: April 2026