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FROMLIST: arm64: dts: qcom: kaanapali: Add iris video node #491

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Merged
shashim-quic merged 1 commit into from
Jan 13, 2026
Merged

FROMLIST: arm64: dts: qcom: kaanapali: Add iris video node #491

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155 changes: 155 additions & 0 deletions arch/arm64/boot/dts/qcom/kaanapali.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@
*/

#include <dt-bindings/clock/qcom,kaanapali-gcc.h>
#include <dt-bindings/clock/qcom,kaanapali-videocc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
#include <dt-bindings/firmware/qcom,scm.h>
Expand Down Expand Up @@ -887,6 +888,160 @@
#reset-cells = <1>;
};

iris: video-codec@2000000 {
compatible = "qcom,kaanapali-iris";

reg = <0x0 0x02000000 0x0 0xf0000>;

interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
<&videocc VIDEO_CC_MVS0_GDSC>,
<&videocc VIDEO_CC_MVS0_VPP0_GDSC>,
<&videocc VIDEO_CC_MVS0_VPP1_GDSC>,
<&videocc VIDEO_CC_MVS0A_GDSC>,
<&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_MMCX>;
power-domain-names = "venus",
"vcodec0",
"vpp0",
"vpp1",
"apv",
"mxc",
"mmcx";

operating-points-v2 = <&iris_opp_table>;

clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>,
<&gcc GCC_VIDEO_AXI1_CLK>,
<&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
<&videocc VIDEO_CC_MVS0_FREERUN_CLK>,
<&videocc VIDEO_CC_MVS0B_CLK>,
<&videocc VIDEO_CC_MVS0_VPP0_CLK>,
<&videocc VIDEO_CC_MVS0_VPP1_CLK>,
<&videocc VIDEO_CC_MVS0A_CLK>;
clock-names = "iface",
"core",
"vcodec0_core",
"iface1",
"core_freerun",
"vcodec0_core_freerun",
"vcodec_bse",
"vcodec_vpp0",
"vcodec_vpp1",
"vcodec_apv";

interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "cpu-cfg",
"video-mem";

memory-region = <&video_mem>;

resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
<&gcc GCC_VIDEO_AXI1_CLK_ARES>,
<&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
<&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
reset-names = "bus0",
"bus1",
"core_freerun_reset",
"vcodec0_core_freerun_reset";

iommus = <&apps_smmu 0x1940 0x0>,
<&apps_smmu 0x1943 0x0>,
<&apps_smmu 0x1944 0x0>,
<&apps_smmu 0x1a20 0x0>;

dma-coherent;

/*
* IRIS firmware is signed by vendors, only
* enable on boards where the proper signed firmware
* is available.
*/
status = "disabled";

iris_opp_table: opp-table {
compatible = "operating-points-v2";

opp-240000000 {
opp-hz = /bits/ 64 <240000000 240000000
240000000 360000000>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
};

opp-338000000 {
opp-hz = /bits/ 64 <338000000 338000000
338000000 507000000>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
};

opp-420000000 {
opp-hz = /bits/ 64 <420000000 420000000
420000000 630000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_svs>;
};

opp-444000000 {
opp-hz = /bits/ 64 <444000000 444000000
444000000 666000000>;
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_svs_l1>;
};

opp-533000000 {
opp-hz = /bits/ 64 <533000000 533000000
533000000 800000000>;
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_nom>;
};

opp-630000000 {
opp-hz = /bits/ 64 <630000000 630000000
630000000 1104000000>;
required-opps = <&rpmhpd_opp_turbo>,
<&rpmhpd_opp_turbo>;
};

opp-800000000 {
opp-hz = /bits/ 64 <800000000 630000000
630000000 1260000000>;
required-opps = <&rpmhpd_opp_turbo_l0>,
<&rpmhpd_opp_turbo_l0>;
};

opp-1000000000 {
opp-hz = /bits/ 64 <1000000000 630000000
850000000 1260000000>;
required-opps = <&rpmhpd_opp_turbo_l1>,
<&rpmhpd_opp_turbo_l1>;
};
};
};

videocc: clock-controller@20f0000 {
compatible = "qcom,kaanapali-videocc";
reg = <0x0 0x20f0000 0x0 0x10000>;
clocks = <&bi_tcxo_div2>,
<&gcc GCC_VIDEO_AHB_CLK>;

power-domains = <&rpmhpd RPMHPD_MMCX>,
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;

#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};

lpass_lpiaon_noc: interconnect@7400000 {
compatible = "qcom,kaanapali-lpass-lpiaon-noc";
reg = <0x0 0x07400000 0x0 0x19080>;
Expand Down