Name		Name	Last commit message	Last commit date
parent directory ..
Makefile		Makefile
chip.v		chip.v
cycle.v		cycle.v
default.gtkw		default.gtkw
readme.md		readme.md
simulate.v		simulate.v
simulate_tb.v		simulate_tb.v
upduino_v2.pcf		upduino_v2.pcf

readme.md

Simulation

Simulate an FPGA circuit.

Requirements

Yosys
Arachne-pnr
Project IceStorm
Icarus Verilog
GTKWave

Usage

make sim

Simulate using iverilog.
make gtkwave

Open the simulation data in gtkwave.

Very loosly based on tomverbeure/upduino