fix(gen_bd): dwidth converter too big; round up AXIS NoC port width

gen_vivado_bd.py

@@ -23,6 +23,7 @@
 """
 
 
+from ir_helper import VALID_TDATA_NUM_BYTES, round_up_to_noc_tdata
 from vivado_bd_helper import (
     arm_ddr_tcl,
     arm_hbm_tcl,
@@ -182,19 +183,14 @@ def dut_stream_noc_tcl(stream_attr: dict[str, dict[str, str]]) -> list[str]:
         tcl += [
             f"""
 set_property -dict [list CONFIG.CONNECTIONS {{{noc_m_port} \
-    {{ write_bw {{{attr["bandwidth"]}}} write_avg_burst {{4}}}}}}] \
+    {{ write_bw {{{float(attr["bandwidth"]) - 50}}} write_avg_burst {{4}}}}}}] \
 [get_bd_intf_pins /axis_noc_dut/{noc_s_port}]
 """
         ]
 
-        # AXIS-NoC only support TDATA_NUM_BYTES of 16, 32, 64
-        valid_tdata_num_bytes = [16, 32, 64]
         # rounds the width up to the nearest supported TDATA_NUM_BYTES
-        if int(attr["width"]) not in valid_tdata_num_bytes:
-            for b in sorted(valid_tdata_num_bytes):
-                if int(attr["width"]) < b:
-                    roundup_num_bytes = b
-                    break
+        if ((int(attr["width"]) + 7) // 8) not in VALID_TDATA_NUM_BYTES:
+            roundup_num_bytes = round_up_to_noc_tdata(attr["width"], True)
 
             tcl += [
                 f"""
@@ -217,7 +213,7 @@ def dut_stream_noc_tcl(stream_attr: dict[str, dict[str, str]]) -> list[str]:
     axis_dwidth_converter_to_dut_{i}
 set_property -dict [list \
     CONFIG.S_TDATA_NUM_BYTES {{{roundup_num_bytes}}} \
-    CONFIG.M_TDATA_NUM_BYTES {{{attr["width"]}}} \
+    CONFIG.M_TDATA_NUM_BYTES {{{(int(attr["width"]) + 7) // 8}}} \
 ] [get_bd_cells axis_dwidth_converter_to_dut_{i}]
 # connect_bd_net [get_bd_pins axis_dwidth_converter_to_dut_{i}/aclk] \
 #     [get_bd_pins clk_wizard_0/clk_out1]

ir_credit_based.py

@@ -10,6 +10,7 @@
 from typing import Any
 
 from ir_helper import (
+    FREQUENCY,
     CreditReturnEnum,
     IREnum,
     create_id_expr,
@@ -453,8 +454,8 @@ def credit_ret_over_noc(
         cc_ret_noc_stream[f"{merged_name}{IREnum.CC_RET.value}"] = {
             "src": srcdest[0],
             "dest": srcdest[1],
-            "width": str(cc_ret_width // 8),
-            "bandwidth": str(cc_ret_width * 250 / 8),
+            "width": str(cc_ret_width),
+            "bandwidth": str(cc_ret_width * FREQUENCY / 8),
         }
 
     for m in grouped_mod_ir["submodules"]:

ir_helper.py

@@ -46,6 +46,35 @@ class CreditReturnEnum(Enum):
     NOC = auto()
 
 
+# AXIS-NoC only support TDATA_NUM_BYTES of 16, 32, 64
+VALID_TDATA_NUM_BYTES = [16, 32, 64]
+FREQUENCY = 250.0
+
+
+def round_up_to_noc_tdata(width: str, byte: bool) -> str:
+    """Rounds the width up to the nearest supported NoC TDATA_NUM_BYTES.
+
+    Returns a string.
+    """
+    # round up to byte
+    if (width_b := (int(width) + 7) // 8) in VALID_TDATA_NUM_BYTES:
+        return str(width_b) if byte else width
+    for b in sorted(VALID_TDATA_NUM_BYTES):
+        if width_b < b:
+            return str(b) if byte else str(b * 8)
+    assert width_b <= VALID_TDATA_NUM_BYTES[-1], f"width ({width}) is too large."
+    raise NotImplementedError
+
+
+def round_up_to_noc_bw(raw_bw: float) -> float:
+    """Rounds the bandwidth up to the nearest supported NoC TDATA_NUM_BYTES.
+
+    Returns a float.
+    """
+    width_b = int(raw_bw / FREQUENCY) * 8
+    return int(round_up_to_noc_tdata(str(width_b), True)) * FREQUENCY
+
+
 def extract_slot_coord(slot_name: str) -> tuple[int, int]:
     """Extracts the x and y coordinates from the slot name.
 

noc_rtl_wrapper.py

@@ -19,6 +19,7 @@
     parse_fifo_params,
     parse_mod,
     parse_top_mod,
+    round_up_to_noc_tdata,
     set_all_pipeline_regions,
 )
 from ir_verilog import create_const_one_driver
@@ -47,11 +48,13 @@ def noc_rtl_wrapper(
 
         # create AXIS-NoC ports
         m_axis_ports = create_m_axis_ports(
-            fifo["name"], fifo_params[IREnum.DATA_WIDTH.value]
+            fifo["name"],
+            round_up_to_noc_tdata(fifo_params[IREnum.DATA_WIDTH.value], False),
         )
         axis_noc_ports += list(m_axis_ports.values())
         s_axis_ports = create_s_axis_ports(
-            fifo["name"], fifo_params[IREnum.DATA_WIDTH.value]
+            fifo["name"],
+            round_up_to_noc_tdata(fifo_params[IREnum.DATA_WIDTH.value], False),
         )
         axis_noc_ports += list(s_axis_ports.values())
 
@@ -161,7 +164,7 @@ def noc_rtl_wrapper(
     import json
     import subprocess
 
-    TEST_DIR = "/home/jakeke/rapidstream-noc/test/build_a48_grb"
+    TEST_DIR = "/home/jakeke/rapidstream-noc/test/build_a48_grb2"
     NOC_PASS_JSON = "noc_pass.json"
     NOC_PASS_WRAPPER_JSON = "noc_pass_wrapper.json"
     with open(f"{TEST_DIR}/{NOC_PASS_JSON}", "r", encoding="utf-8") as file:

run_noc_pass.py

@@ -14,7 +14,13 @@
 
 from device import Device
 from gen_vivado_bd import gen_arm_bd_hbm
-from ir_helper import parse_floorplan, parse_inter_slot, parse_top_mod
+from ir_helper import (
+    FREQUENCY,
+    parse_floorplan,
+    parse_inter_slot,
+    parse_top_mod,
+    round_up_to_noc_tdata,
+)
 from noc_pass import greedy_selector, ilp_noc_selector, random_selector
 from noc_rtl_wrapper import noc_rtl_wrapper
 from tcl_helper import (
@@ -75,7 +81,6 @@ class SelectorEnum(Enum):
         top_mod_name = sys.argv[6]
 
     # currently hard-coded parameters
-    FREQUENCY = 250.0
     IMPL_FREQUENCY = "300.0"
     HBM_INIT_FILE = "/home/jakeke/rapidstream-noc/test/serpens_hbm48_nasa4704.mem"
     TB_FILE = "/home/jakeke/rapidstream-noc/test/serpens_tb_a48_new.sv"
@@ -250,7 +255,7 @@ class SelectorEnum(Enum):
             noc_stream_attr[f"m_axis_{s}"] = {
                 "dest": f"s_axis_{s}",
                 "bandwidth": str(streams_bw[s]),
-                "width": str((streams_widths[s] + 7) // 8),  # round up to bytes
+                "width": round_up_to_noc_tdata(str(streams_widths[s]), False),
             }
 
         for s, attr in cc_ret_noc_stream.items():

vivado_bd_helper.py

@@ -638,7 +638,7 @@ def arm_hbm_tcl(mmap_ports: dict[str, dict[str, int]], fpd: bool) -> list[str]:
         if not fpd and i in PS_RPU_PORT:
             tcl += [
                 "\
-    M00_AXI {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}"
+    M00_AXI {read_bw {0} write_bw {50} read_avg_burst {4} write_avg_burst {4}}"
             ]
 
         arm_s_axi = f"S{i:02d}_AXI"
@@ -647,7 +647,7 @@ def arm_hbm_tcl(mmap_ports: dict[str, dict[str, int]], fpd: bool) -> list[str]:
             if attr["write_bw"] > 0:
                 tcl += [
                     f"""\
-    HBM{attr["bank"] // 2}_PORT{(attr["bank"] % 2) * 2} {{read_bw {{50}} write_bw {{0}}\
+    HBM{attr["bank"] // 2}_PORT{(attr["bank"] % 2) * 2} {{read_bw {{5}} write_bw {{0}}\
     read_avg_burst {{4}} write_avg_burst {{4}}}}"""
                 ]
         tcl += [f"}}] [get_bd_intf_pins $noc_hbm_0/{arm_s_axi}]"]