feat(axplat_crates): upgrade uart_16550 to 0.5.0

components/axplat_crates/platforms/axplat-loongarch64-qemu-virt/Cargo.toml

@@ -24,7 +24,7 @@ lazyinit = "0.2"
 log = "0.4"
 loongArch64 = "0.2.4"
 page_table_entry = "0.6"
-uart_16550 = "0.4.0"
+uart_16550 = "0.5"
 
 axconfig-macros = "0.2"
 axcpu = { workspace = true }

components/axplat_crates/platforms/axplat-loongarch64-qemu-virt/src/console.rs

@@ -1,19 +1,19 @@
-use axplat::{
-    console::ConsoleIf,
-    mem::{pa, phys_to_virt},
-};
+use axplat::console::ConsoleIf;
 use kspin::SpinNoIrq;
 use lazyinit::LazyInit;
-use uart_16550::MmioSerialPort;
+use uart_16550::{Config, Uart16550, backend::MmioBackend};
 
-use crate::config::devices::UART_PADDR;
+use crate::config::{devices::UART_PADDR, plat::PHYS_VIRT_OFFSET};
 
-static UART: LazyInit<SpinNoIrq<MmioSerialPort>> = LazyInit::new();
+static UART: LazyInit<SpinNoIrq<Uart16550<MmioBackend>>> = LazyInit::new();
 
 pub(crate) fn init_early() {
     UART.init_once({
-        let mut uart = unsafe { MmioSerialPort::new(phys_to_virt(pa!(UART_PADDR)).as_usize()) };
-        uart.init();
+        let mut uart =
+            unsafe { Uart16550::new_mmio((UART_PADDR + PHYS_VIRT_OFFSET) as *mut u8, 1) }.unwrap();
+        uart.init(Config::default())
+            .expect("Failed to initialize UART");
+        uart.test_loopback().expect("Failed to test UART loopback");
         SpinNoIrq::new(uart)
     });
 }
@@ -27,11 +27,8 @@ impl ConsoleIf for ConsoleIfImpl {
         for &c in bytes {
             let mut uart = UART.lock();
             match c {
-                b'\n' => {
-                    uart.send_raw(b'\r');
-                    uart.send_raw(b'\n');
-                }
-                c => uart.send_raw(c),
+                b'\n' => uart.send_bytes_exact(b"\r\n"),
+                c => uart.send_bytes_exact(&[c]),
             }
         }
     }
@@ -40,15 +37,10 @@ impl ConsoleIf for ConsoleIfImpl {
     /// Returns the number of bytes read.
     fn read_bytes(bytes: &mut [u8]) -> usize {
         let mut uart = UART.lock();
-        for (i, byte) in bytes.iter_mut().enumerate() {
-            match uart.try_receive() {
-                Ok(c) => *byte = c,
-                Err(_) => return i,
-            }
-        }
-        bytes.len()
+        uart.try_receive_bytes(bytes)
     }
 
+    /// Returns the IRQ number for the console, if applicable.
     #[cfg(feature = "irq")]
     fn irq_num() -> Option<usize> {
         Some(crate::config::devices::UART_IRQ)

components/axplat_crates/platforms/axplat-riscv64-qemu-virt/Cargo.toml

@@ -25,7 +25,7 @@ riscv = "0.16"
 riscv_goldfish = { version = "0.1", optional = true }
 riscv_plic = { version = "0.2", optional = true }
 sbi-rt = { version = "0.0.3", features = ["legacy"] }
-uart_16550 = "0.4.0"
+uart_16550 = "0.5.0"
 
 axconfig-macros = "0.2"
 axcpu = { workspace = true }

components/axplat_crates/platforms/axplat-riscv64-qemu-virt/src/console.rs

@@ -1,16 +1,19 @@
 use axplat::console::ConsoleIf;
 use kspin::SpinNoIrq;
 use lazyinit::LazyInit;
-use uart_16550::MmioSerialPort;
+use uart_16550::{Config, Uart16550, backend::MmioBackend};
 
 use crate::config::{devices::UART_PADDR, plat::PHYS_VIRT_OFFSET};
 
-static UART: LazyInit<SpinNoIrq<MmioSerialPort>> = LazyInit::new();
+static UART: LazyInit<SpinNoIrq<Uart16550<MmioBackend>>> = LazyInit::new();
 
 pub(crate) fn init_early() {
     UART.init_once({
-        let mut uart = unsafe { MmioSerialPort::new(UART_PADDR + PHYS_VIRT_OFFSET) };
-        uart.init();
+        let mut uart =
+            unsafe { Uart16550::new_mmio((UART_PADDR + PHYS_VIRT_OFFSET) as *mut u8, 1) }.unwrap();
+        uart.init(Config::default())
+            .expect("Failed to initialize UART");
+        uart.test_loopback().expect("Failed to test UART loopback");
         SpinNoIrq::new(uart)
     });
 }
@@ -24,11 +27,8 @@ impl ConsoleIf for ConsoleIfImpl {
         for &c in bytes {
             let mut uart = UART.lock();
             match c {
-                b'\n' => {
-                    uart.send_raw(b'\r');
-                    uart.send_raw(b'\n');
-                }
-                c => uart.send_raw(c),
+                b'\n' => uart.send_bytes_exact(b"\r\n"),
+                c => uart.send_bytes_exact(&[c]),
             }
         }
     }
@@ -37,13 +37,7 @@ impl ConsoleIf for ConsoleIfImpl {
     /// Returns the number of bytes read.
     fn read_bytes(bytes: &mut [u8]) -> usize {
         let mut uart = UART.lock();
-        for (i, byte) in bytes.iter_mut().enumerate() {
-            match uart.try_receive() {
-                Ok(c) => *byte = c,
-                Err(_) => return i,
-            }
-        }
-        bytes.len()
+        uart.try_receive_bytes(bytes)
     }
 
     /// Returns the IRQ number for the console, if applicable.

components/axplat_crates/platforms/axplat-x86-pc/Cargo.toml

@@ -35,7 +35,7 @@ x86_64 = "0.15.2"
 x2apic = "0.5"
 multiboot = "0.8"
 raw-cpuid = "11.5"
-uart_16550 = "0.4"
+uart_16550 = "0.5"
 x86_rtc = { version = "0.1", optional = true }
 
 [package.metadata.docs.rs]