Created skeleton for SN76489 PSG chip implementation

info.yaml

@@ -5,10 +5,9 @@ project:
 
 # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. 
 # Source files must be in ./src and you must list each source file separately
-#  source_files:        
-#    - counter.v
-#    - decoder.v
-#  top_module:  "tt_um_example"      # Put the name of your top module here, must start with "tt_um_". Make it unique by including your github username
+  source_files:
+    - tt_um_rejunity_sn76489.v
+  top_module:  "tt_um_rejunity_sn76489"      # Put the name of your top module here, must start with "tt_um_". Make it unique by including your github username
 
 # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"    # Valid values: 1x1, 1x2, 2x2, 4x2 or 8x2
@@ -18,42 +17,41 @@ yaml_version: 4
 
 # As everyone will have access to all designs, try to make it easy for someone new to your design to know what
 # it does and how to operate it. This info will be automatically collected and used to make a datasheet for the chip.
-#
-# Here is a great example: https://github.com/davidsiaw/tt02-davidsiaw-stackcalc/blob/38c5647f83aad2aec675d566aa3d67b98f0aac81/info.yaml
 documentation: 
-  author:       ""      # Your name
-  title:        ""      # Project title
-  language:     "Wokwi" # other examples include Verilog, Amaranth, VHDL, etc
-  description:  ""      # Short description of what your project does
+  author:       "rej"
+  title:        "Classic 8-bit era Programmable Sound Generator SN76489"
+  language:     "Verilog"
+  description:  "The SN76489 Digital Complex Sound Generator (DCSG) is a programmable sound generator chip from Texas Instruments."
 
 # Longer description of how the project works. You can use standard markdown format.
   how_it_works: |
       Explain how your project works
+      https://en.wikipedia.org/wiki/Texas_Instruments_SN76489
 
 # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
   how_to_test:  |
       Explain how to test your project
 
 # A description of what the inputs do (e.g. red button, SPI CLK, SPI MOSI, etc).
   inputs:               
+    - data0
+    - data1
+    - data2
+    - data3
+    - data4
+    - data5
+    - data6
+    - data7
+# A description of what the outputs do (e.g. status LED, SPI MISO, etc)
+  outputs:
+    - snd_out
     - none
     - none
     - none
     - none
     - none
     - none
     - none
-    - none
-# A description of what the outputs do (e.g. status LED, SPI MISO, etc)
-  outputs:
-    - segment a
-    - segment b
-    - segment c
-    - segment d
-    - segment e
-    - segment f
-    - segment g
-    - dot
 # A description of what the bidirectional I/O pins do (e.g. I2C SDA, I2C SCL, etc)
   bidirectional:
     - none
@@ -66,9 +64,9 @@ documentation:
     - none
 
 # The following fields are optional
-  tag:          ""      # comma separated list of tags: test, encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator,
-  external_hw:  ""      # Describe any external hardware needed
-  discord:      ""      # Your discord handle, used for communication and automatically assigning tapeout role after a submission
-  doc_link:     ""      # URL to longer form documentation, eg the README.md in your repository
-  clock_hz:     0       # Clock frequency in Hz (if required)
-  picture:      ""      # relative path to a picture in your repository (must be 512kb or less)
+  tag:          "psg, music, sound" # comma separated list of tags: test, encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator,
+  external_hw:  ""        # Describe any external hardware needed
+  discord:      "rzioma"  # Your discord handle, used for communication and automatically assigning tapeout role after a submission
+  doc_link:     ""        # URL to longer form documentation, eg the README.md in your repository
+  clock_hz:     50000000  # Clock frequency in Hz (if required)
+  picture:      ""        # relative path to a picture in your repository (must be 512kb or less)

src/Makefile

@@ -0,0 +1,36 @@
+# Makefile
+# See https://docs.cocotb.org/en/stable/quickstart.html for more info
+
+# defaults
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+
+# normal simulation
+ifneq ($(GATES),yes)
+
+# this is the only part you should need to modify:
+VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/tt_um_rejunity_sn76489.v
+
+else
+
+# gate level simulation requires some extra setup, you shouldn't need to touch this
+COMPILE_ARGS    += -DGL_TEST
+COMPILE_ARGS    += -DFUNCTIONAL
+COMPILE_ARGS    += -DUSE_POWER_PINS
+COMPILE_ARGS    += -DSIM
+COMPILE_ARGS    += -DUNIT_DELAY=\#1
+VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+
+# this gets copied in by the GDS action workflow
+VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/gate_level_netlist.v
+endif
+
+# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
+TOPLEVEL = tb
+
+# MODULE is the basename of the Python test file
+MODULE = test
+
+# include cocotb's make rules to take care of the simulator setup
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/tb.v

@@ -0,0 +1,46 @@
+`default_nettype none
+`timescale 1ns/1ps
+
+/*
+this testbench just instantiates the module and makes some convenient wires
+that can be driven / tested by the cocotb test.py
+*/
+
+// testbench is controlled by test.py
+module tb ();
+
+    // this part dumps the trace to a vcd file that can be viewed with GTKWave
+    initial begin
+        $dumpfile ("tb.vcd");
+        $dumpvars (0, tb);
+        #1;
+    end
+
+    // wire up the inputs and outputs
+    wire [7:0] ui_in;
+    wire [7:0] uo_out;
+    wire [7:0] uio_in;
+    wire [7:0] uio_out;
+    wire [7:0] uio_oe;
+    wire clk;
+    wire rst_n;
+    wire ena;
+
+    tt_um_rejunity_sn76489 tt_um_rejunity_sn76489_uut 
+    (
+        // include power ports for the Gate Level test
+        `ifdef GL_TEST
+            .VPWR( 1'b1),
+            .VGND( 1'b0),
+        `endif
+        .ui_in      (ui_in),    // Dedicated inputs
+        .uo_out     (uo_out),   // Dedicated outputs
+        .uio_in     (uio_in),   // IOs: Input path
+        .uio_out    (uio_out),  // IOs: Output path
+        .uio_oe     (uio_oe),   // IOs: Enable path (active high: 0=input, 1=output)
+        .ena        (ena),      // enable - goes high when design is selected
+        .clk        (clk),      // clock
+        .rst_n      (rst_n)     // not reset
+    );
+
+endmodule

src/test.py

@@ -0,0 +1,26 @@
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, FallingEdge, Timer, ClockCycles
+
+
+
+@cocotb.test()
+async def test_rule110_automata(dut):
+
+    dut._log.info("start")
+    clock = Clock(dut.clk, 10, units="us")
+    cocotb.start_soon(clock.start())
+
+    dut._log.info("reset")
+    dut.rst_n.value = 0
+    await ClockCycles(dut.clk, 10)
+    dut.rst_n.value = 1
+
+    dut._log.info("run")
+    for i in range(32):
+        await ClockCycles(dut.clk, 1)
+        print(
+            #dut.uio_out.value,
+            dut.uo_out.value)
+
+    dut._log.info("done")

src/tt_um_rejunity_sn76489.v

@@ -0,0 +1,35 @@
+`default_nettype none
+
+module tt_um_rejunity_sn76489 #( parameter NUM_VOICES = 3 ) (
+    input  wire [7:0] ui_in,    // Dedicated inputs - connected to the input switches
+    output wire [7:0] uo_out,   // Dedicated outputs - connected to the 7 segment display
+    input  wire [7:0] uio_in,   // IOs: Bidirectional Input path
+    output wire [7:0] uio_out,  // IOs: Bidirectional Output path
+    output wire [7:0] uio_oe,   // IOs: Bidirectional Enable path (active high: 0=input, 1=output)
+    input  wire       ena,      // will go high when the design is enabled
+    input  wire       clk,      // clock
+    input  wire       rst_n     // reset_n - low to reset
+);
+    assign uo_out[7:0] = {8{1'b0}};
+    assign uio_oe[7:0] = {8{1'b1}}; // Bidirectional path set to output
+    assign uio_out[7:0] = {8{1'b0}};
+    wire reset = ! rst_n;
+
+    always @(posedge clk) begin
+        if (reset) begin
+        end else begin
+        end
+    end
+
+    genvar i;
+    generate
+        for (i = 0; i < NUM_VOICES; i = i + 1) begin
+        end
+    endgenerate
+
+    wire snd_out;
+    assign snd_out = 0;
+    assign uo_out[0] = snd_out;
+
+
+endmodule