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SystemVerilog improvements and fixes (#797)
* SV: Fix some more tests * SV: Fix extract from length 1 bitvectors SystemVerilog does not allow extracting the bit from a length 1 bitvector, i.e. the following results in an error ``` x[n][0] ``` To solve this, extract requires an extra argument which is the length of the bitvector being extracted from, so we can detect the `Extract (0, 0, 1, bv)` case when generating SystemVerilog * SV: Allow generating toplevel module with clk and reset signals * SV: Refactor attribute handling
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