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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1 +1,2 @@ | ||
| $include <concurrency_interface/v1.sail> | ||
| $include <concurrency_interface/read_write.sail> | ||
| $include <concurrency_interface/barrier.sail> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,92 @@ | ||
| /*==========================================================================*/ | ||
| /* Sail */ | ||
| /* */ | ||
| /* Sail and the Sail architecture models here, comprising all files and */ | ||
| /* directories except the ASL-derived Sail code in the aarch64 directory, */ | ||
| /* are subject to the BSD two-clause licence below. */ | ||
| /* */ | ||
| /* The ASL derived parts of the ARMv8.3 specification in */ | ||
| /* aarch64/no_vector and aarch64/full are copyright ARM Ltd. */ | ||
| /* */ | ||
| /* Copyright (c) 2013-2021 */ | ||
| /* Kathyrn Gray */ | ||
| /* Shaked Flur */ | ||
| /* Stephen Kell */ | ||
| /* Gabriel Kerneis */ | ||
| /* Robert Norton-Wright */ | ||
| /* Christopher Pulte */ | ||
| /* Peter Sewell */ | ||
| /* Alasdair Armstrong */ | ||
| /* Brian Campbell */ | ||
| /* Thomas Bauereiss */ | ||
| /* Anthony Fox */ | ||
| /* Jon French */ | ||
| /* Dominic Mulligan */ | ||
| /* Stephen Kell */ | ||
| /* Mark Wassell */ | ||
| /* Alastair Reid (Arm Ltd) */ | ||
| /* */ | ||
| /* All rights reserved. */ | ||
| /* */ | ||
| /* This work was partially supported by EPSRC grant EP/K008528/1 <a */ | ||
| /* href="http://www.cl.cam.ac.uk/users/pes20/rems">REMS: Rigorous */ | ||
| /* Engineering for Mainstream Systems</a>, an ARM iCASE award, EPSRC IAA */ | ||
| /* KTF funding, and donations from Arm. This project has received */ | ||
| /* funding from the European Research Council (ERC) under the European */ | ||
| /* Union’s Horizon 2020 research and innovation programme (grant */ | ||
| /* agreement No 789108, ELVER). */ | ||
| /* */ | ||
| /* This software was developed by SRI International and the University of */ | ||
| /* Cambridge Computer Laboratory (Department of Computer Science and */ | ||
| /* Technology) under DARPA/AFRL contracts FA8650-18-C-7809 ("CIFV") */ | ||
| /* and FA8750-10-C-0237 ("CTSRD"). */ | ||
| /* */ | ||
| /* Redistribution and use in source and binary forms, with or without */ | ||
| /* modification, are permitted provided that the following conditions */ | ||
| /* are met: */ | ||
| /* 1. Redistributions of source code must retain the above copyright */ | ||
| /* notice, this list of conditions and the following disclaimer. */ | ||
| /* 2. Redistributions in binary form must reproduce the above copyright */ | ||
| /* notice, this list of conditions and the following disclaimer in */ | ||
| /* the documentation and/or other materials provided with the */ | ||
| /* distribution. */ | ||
| /* */ | ||
| /* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ | ||
| /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ | ||
| /* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ | ||
| /* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ | ||
| /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ | ||
| /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ | ||
| /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ | ||
| /* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ | ||
| /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ | ||
| /* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ | ||
| /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ | ||
| /* SUCH DAMAGE. */ | ||
| /*==========================================================================*/ | ||
|
|
||
| $sail_internal | ||
|
|
||
| $ifndef _CONCURRENCY_INTERFACE_COMMON | ||
| $define _CONCURRENCY_INTERFACE_COMMON | ||
|
|
||
| $ifdef _DEFAULT_DEC | ||
| $include <vector_dec.sail> | ||
| $else | ||
| $include <vector_inc.sail> | ||
| $endif | ||
|
|
||
| $include <option.sail> | ||
| $include <result.sail> | ||
| $include <concurrency_interface/emulator_memory.sail> | ||
|
|
||
| val sail_instr_announce | ||
| = pure { ocaml: "Platform.instr_announce", c: "platform_instr_announce", _: "instr_announce" } | ||
| : forall 'n, 'n > 0. | ||
| bits('n) -> unit | ||
|
|
||
| $target_set emulator_or_isla isla c ocaml interpreter | ||
| $target_set emulator c ocaml interpreter | ||
| $target_set prover lem coq | ||
|
|
||
| $endif |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,152 @@ | ||
| /*==========================================================================*/ | ||
| /* Sail */ | ||
| /* */ | ||
| /* Sail and the Sail architecture models here, comprising all files and */ | ||
| /* directories except the ASL-derived Sail code in the aarch64 directory, */ | ||
| /* are subject to the BSD two-clause licence below. */ | ||
| /* */ | ||
| /* The ASL derived parts of the ARMv8.3 specification in */ | ||
| /* aarch64/no_vector and aarch64/full are copyright ARM Ltd. */ | ||
| /* */ | ||
| /* Copyright (c) 2013-2021 */ | ||
| /* Kathyrn Gray */ | ||
| /* Shaked Flur */ | ||
| /* Stephen Kell */ | ||
| /* Gabriel Kerneis */ | ||
| /* Robert Norton-Wright */ | ||
| /* Christopher Pulte */ | ||
| /* Peter Sewell */ | ||
| /* Alasdair Armstrong */ | ||
| /* Brian Campbell */ | ||
| /* Thomas Bauereiss */ | ||
| /* Anthony Fox */ | ||
| /* Jon French */ | ||
| /* Dominic Mulligan */ | ||
| /* Stephen Kell */ | ||
| /* Mark Wassell */ | ||
| /* Alastair Reid (Arm Ltd) */ | ||
| /* */ | ||
| /* All rights reserved. */ | ||
| /* */ | ||
| /* This work was partially supported by EPSRC grant EP/K008528/1 <a */ | ||
| /* href="http://www.cl.cam.ac.uk/users/pes20/rems">REMS: Rigorous */ | ||
| /* Engineering for Mainstream Systems</a>, an ARM iCASE award, EPSRC IAA */ | ||
| /* KTF funding, and donations from Arm. This project has received */ | ||
| /* funding from the European Research Council (ERC) under the European */ | ||
| /* Union’s Horizon 2020 research and innovation programme (grant */ | ||
| /* agreement No 789108, ELVER). */ | ||
| /* */ | ||
| /* This software was developed by SRI International and the University of */ | ||
| /* Cambridge Computer Laboratory (Department of Computer Science and */ | ||
| /* Technology) under DARPA/AFRL contracts FA8650-18-C-7809 ("CIFV") */ | ||
| /* and FA8750-10-C-0237 ("CTSRD"). */ | ||
| /* */ | ||
| /* Redistribution and use in source and binary forms, with or without */ | ||
| /* modification, are permitted provided that the following conditions */ | ||
| /* are met: */ | ||
| /* 1. Redistributions of source code must retain the above copyright */ | ||
| /* notice, this list of conditions and the following disclaimer. */ | ||
| /* 2. Redistributions in binary form must reproduce the above copyright */ | ||
| /* notice, this list of conditions and the following disclaimer in */ | ||
| /* the documentation and/or other materials provided with the */ | ||
| /* distribution. */ | ||
| /* */ | ||
| /* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ | ||
| /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ | ||
| /* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ | ||
| /* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ | ||
| /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ | ||
| /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ | ||
| /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ | ||
| /* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ | ||
| /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ | ||
| /* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ | ||
| /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ | ||
| /* SUCH DAMAGE. */ | ||
| /*==========================================================================*/ | ||
|
|
||
| $sail_internal | ||
|
|
||
| $ifndef _EMULATOR_MEMORY | ||
|
|
||
| $ifdef _DEFAULT_DEC | ||
| $include <vector_dec.sail> | ||
| $else | ||
| $include <vector_inc.sail> | ||
| $endif | ||
|
|
||
| //! Read memory | ||
| $iftarget isla | ||
| val read_mem# = monadic "read_mem" : forall ('a: Type) 'n 'addrsize, 'n >= 0 & 'addrsize in {32, 64}. | ||
| ('a, int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n) | ||
| $else | ||
| val read_mem# : forall ('a: Type) 'n 'addrsize, 'n >= 0 & 'addrsize in {32, 64}. | ||
| ('a, int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n) | ||
|
|
||
| val __read_mem# = monadic "emulator_read_mem" : forall 'n 'addrsize, 'n >= 0 & 'addrsize in {32, 64}. | ||
| (int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n) | ||
|
|
||
| function read_mem#(_, addrsize, addr, n) = __read_mem#(addrsize, addr, n) | ||
| $endif | ||
|
|
||
| //! Read memory, but signal to the emulator that this is an ifetch read | ||
| $iftarget isla | ||
| val read_mem_ifetch# = monadic "read_mem_ifetch" : forall ('a: Type) 'n 'addrsize, 'n >= 0 & 'addrsize in {32, 64}. | ||
| ('a, int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n) | ||
| $else | ||
| val read_mem_ifetch# : forall ('a: Type) 'n 'addrsize, 'n >= 0 & 'addrsize in {32, 64}. | ||
| ('a, int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n) | ||
|
|
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| val __read_mem_ifetch# = monadic "emulator_read_mem_ifetch" : forall 'n 'addrsize, 'n >= 0 & 'addrsize in {32, 64}. | ||
| (int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n) | ||
|
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| function read_mem_ifetch#(_, addrsize, addr, n) = __read_mem_ifetch#(addrsize, addr, n) | ||
| $endif | ||
|
|
||
| //! Read memory, and signal to the emulator that this read should be treated as an exclusive access | ||
| $iftarget isla | ||
| val read_mem_exclusive# = monadic "read_mem_exclusive" : forall ('a: Type) 'n 'addrsize, 'n >= 0 & 'addrsize in {32, 64}. | ||
| ('a, int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n) | ||
| $else | ||
| val read_mem_exclusive# : forall ('a: Type) 'n 'addrsize, 'n >= 0 & 'addrsize in {32, 64}. | ||
| ('a, int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n) | ||
|
|
||
| val __read_mem_exclusive# = monadic "emulator_read_mem_exclusive" : forall 'n 'addrsize, 'n >= 0 & 'addrsize in {32, 64}. | ||
| (int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n) | ||
|
|
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| function read_mem_exclusive#(_, addrsize, addr, n) = __read_mem_exclusive#(addrsize, addr, n) | ||
| $endif | ||
|
|
||
| //! Write memory | ||
| $iftarget isla | ||
| val write_mem# = monadic "write_mem" : forall ('a: Type) 'n 'addrsize, 'n > 0 & 'addrsize in {32, 64}. | ||
| ('a, int('addrsize), bits('addrsize), int('n), bits(8 * 'n)) -> bool | ||
| $else | ||
| val write_mem# : forall ('a: Type) 'n 'addrsize, 'n > 0 & 'addrsize in {32, 64}. | ||
| ('a, int('addrsize), bits('addrsize), int('n), bits(8 * 'n)) -> bool | ||
|
|
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| val __write_mem# = monadic "emulator_write_mem" : forall 'n 'addrsize, 'n > 0 & 'addrsize in {32, 64}. | ||
| (int('addrsize), bits('addrsize), int('n), bits(8 * 'n)) -> bool | ||
|
|
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| function write_mem#(_, addrsize, addr, n, value) = __write_mem#(addrsize, addr, n, value) | ||
| $endif | ||
|
|
||
| //! Write memory, and signal to the emulator that this read should be treated as an exclusive access | ||
| $iftarget isla | ||
| val write_mem_exclusive# = monadic "write_mem_exclusive" : forall ('a: Type) 'n 'addrsize, 'n > 0 & 'addrsize in {32, 64}. | ||
| ('a, int('addrsize), bits('addrsize), int('n), bits(8 * 'n)) -> bool | ||
| $else | ||
| val write_mem_exclusive# : forall ('a: Type) 'n 'addrsize, 'n > 0 & 'addrsize in {32, 64}. | ||
| ('a, int('addrsize), bits('addrsize), int('n), bits(8 * 'n)) -> bool | ||
|
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| val __write_mem_exclusive# = monadic "emulator_write_mem_exclusive" : forall 'n 'addrsize, 'n > 0 & 'addrsize in {32, 64}. | ||
| (int('addrsize), bits('addrsize), int('n), bits(8 * 'n)) -> bool | ||
|
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| function write_mem_exclusive#(_, addrsize, addr, n, value) = __write_mem_exclusive#(addrsize, addr, n, value) | ||
| $endif | ||
|
|
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| val read_tag# = monadic "read_tag_bool" : forall 'addrsize, 'addrsize in {32, 64}. (int('addrsize), bits('addrsize)) -> bool | ||
|
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| val write_tag# = monadic "write_tag_bool" : forall 'addrsize, 'addrsize in {32, 64}. (int('addrsize), bits('addrsize), bool) -> unit | ||
|
|
||
| $endif |
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