honour the text wrapping

src/riscv-integration.adoc

@@ -32,11 +32,12 @@ where address 2^XLENMAX^ - 1 is within the bounds.
 === Programmer's Model for Zcheri_purecap
 
 For {cheri_base_ext_name}, the 32 unprivileged *x* registers of the base
-integer ISA are extended so that they are able to hold a capability as well as renamed to *c* registers. Therefore,
-each *c* register is CLEN bits wide and has an out of band tag bit. The *x*
-notation refers to the address field of the capability in an unprivileged
-register while the *c* notation is used to refer to the full capability (i.e.
-address, metadata and tag) held in the same unprivileged register.
+integer ISA are extended so that they are able to hold a capability as well
+as renamed to *c* registers. Therefore, each *c* register is CLEN bits wide
+and has an out of band tag bit. The *x* notation refers to the address field
+of the capability in an unprivileged register while the *c* notation is used
+to refer to the full capability (i.e. address, metadata and tag) held in the
+same unprivileged register.
 
 Register *c0* is hardwired with all bits, including the capability metadata and
 tag, equal to 0. In other words, *c0* is hardwired to the <<null-cap>>