Fix observing CHERI execution mode code

riscv · Jan 13, 2025 · 17823af · 17823af
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diff --git a/src/contributors.adoc b/src/contributors.adoc
@@ -36,5 +36,6 @@ This RISC-V specification has been contributed to directly or indirectly by:
 * Ricki Tura <ricki[email protected]>
 * Robert N. M. Watson <robert[email protected]>
 * Toby Wenman <toby[email protected]>
+* Jay Williams  <jay[email protected]>
 * Jonathan Woodruff <jonathan[email protected]>
 * Jason Zhijingcheng Yu <yu[email protected]>
diff --git a/src/riscv-hybrid-integration.adoc b/src/riscv-hybrid-integration.adoc
@@ -109,7 +109,7 @@ for {cheri_cap_mode_name} and {INT_MODE_VALUE} for
 
 ```
 auipc c1, 0
-gctag x1, c1
+gcmode x1, c1
 ```
 
 [#section_hybrid_ext_instructions]