Rename AUIPCC, and fix some other minor issues

src/csv/CHERI_ISA.csv

@@ -5,14 +5,14 @@
 "C.SCSP","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","✔","","C2","","C.FSWSP","C.FSDSP","Store cap via cap, SP relative ","","","","","","","",""
 "C.LC","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","✔","","C0","","C.FLW","C.FLD","Load cap via cap","","","","","","","",""
 "C.SC","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","✔","","C0","","C.FSW","C.FSD","Store cap via cap ","","","","","","","",""
-"C.LWSP","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C2","","C.LWSP","C.LWSP","Load word via cap, SP relative","","","","","","","",""
-"C.SWSP","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C2","","C.SWSP","C.SWSP","Store word via cap, SP relative","","","","","","","",""
-"C.LW","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.LW","C.LW","Load word via cap","","","","","","","",""
-"C.SW","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.SW","C.SW","Store word via cap ","","","","","","","",""
-"C.LD","","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.LD","C.LD","Load word via cap","","","","","","","",""
-"C.SD","","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.SD","C.SD","Store word via cap ","","","","","","","",""
-"C.LDSP","","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.LDSP","C.LDSP","Load word via cap","","","","","","","",""
-"C.SDSP","","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.SDSP","C.SDSP","Store word via cap ","","","","","","","",""
+"C.LWSP","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C2","","C.LWSP","C.LWSP","Load word via cap, SP relative","","","","","","","",""
+"C.SWSP","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C2","","C.SWSP","C.SWSP","Store word via cap, SP relative","","","","","","","",""
+"C.LW","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.LW","C.LW","Load word via cap","","","","","","","",""
+"C.SW","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.SW","C.SW","Store word via cap ","","","","","","","",""
+"C.LD","","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.LD","C.LD","Load word via cap","","","","","","","",""
+"C.SD","","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.SD","C.SD","Store word via cap ","","","","","","","",""
+"C.LDSP","","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.LDSP","C.LDSP","Load word via cap","","","","","","","",""
+"C.SDSP","","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.SDSP","C.SDSP","Store word via cap ","","","","","","","",""
 "LB","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","0","LOAD","","","","Load signed byte ","","","","","","","",""
 "LH","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","1","LOAD","","","","Load signed half ","","","","","","","",""
 "C.LH","✔","✔","","","","✔","✔","Both","","","","","✔","","","","","","","","","","","C0","","","","Load signed half ","","","","","","","",""
@@ -29,8 +29,7 @@
 "C.SH","✔","✔","","","","✔","✔","Both","","","","","✔","","","","","","","","","","","STORE","","","","Store half ","","","","","","","",""
 "SW","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","STORE","","","","Store word ","","","","","","","",""
 "SD","","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","STORE","","","","Store double ","","","","","","","",""
-"AUIPC","✔","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","AUIPC","","","","Add immediate to PCC address","","","","","","","",""
-"AUIPCC","✔","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","AUIPC","","AUIPC","AUIPC","Add immediate to PCC address, representability check","","","","","","","",""
+"AUIPC","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","AUIPC","","","","Add immediate to PCC address","","","","","","","",""
 "CINCOFFSET","✔","✔","","","","","✔","Both","","","","","","","","","","","","","","","","OP","R-type","","","Increment cap address by register, representability check","","","","","","","",""
 "CINCOFFSETIMM","✔","✔","","","","","✔","Both","","","","","","","","","","","","","","","","OP","I-type","","","Increment cap address by immediate, representability check","","","","","","","",""
 "CSETADDR","✔","✔","","","","","✔","Both","","","","","","","","","","","","","","","","OP","R-type","","","Replace capability address, representability check","","","","","","","",""

src/insns/auipcc_32bit.adoc → src/insns/auipc_32bit.adoc

@@ -3,16 +3,11 @@
 [#AUIPC,reftext="AUIPC"]
 ==== AUIPC
 
-See <<AUIPCC>>
-
-[#AUIPCC,reftext="AUIPCC"]
-==== AUIPCC
-
 Synopsis::
 Add upper immediate to *pc*/<<pcc>>
 
 Capability Mode Mnemonic::
-`auipcc cd, imm`
+`auipc cd, imm`
 
 Legacy Mode Mnemonic::
 `auipc rd, imm`
@@ -22,7 +17,7 @@ include::wavedrom/rv64_lui-auipc.adoc[]
 
 Capability Mode Description::
 Form a 32-bit offset from the 20-bit immediate filling the lowest 12 bits with
-zeros. Increment the address of the <<AUIPCC>> instruction's <<pcc>> by the
+zeros. Increment the address of the AUIPC instruction's <<pcc>> by the
 32-bit offset, then write the output capability to `cd`. The tag bit of the
 output capability is 0 if the incremented address is outside the <<pcc>>'s
 <<section_cap_representable_check>>.
@@ -34,13 +29,13 @@ the result in register `rd`.
 
 include::pcrel_debug_warning.adoc[]
 
-Prerequisites for AUIPCC::
+Prerequisites for Capability Mode::
 {cheri_base_ext_name}
 
-Prerequisites for AUIPC::
+Prerequisites for Legacy Mode::
 {cheri_legacy_ext_name}
 
-Operation for AUIPCC::
+Operation for AUIPC::
 +
 --
 TODO

src/insns/csetmode_32bit.adoc

@@ -1,6 +1,6 @@
 <<<
 
-[#csetmode]
+[#csetmode, reftext="CSETMODE"]
 ==== CSETMODE
 
 ifdef::cheri_v9_annotations[]

src/insns/load_16bit_fp_dp.adoc

@@ -2,10 +2,6 @@
 [#C_FLD,reftext="C.FLD"]
 ==== C.FLD
 
-See <<C.FLDSP>>.
-
-<<<
-
 [#C_FLDSP,reftext="C.FLDSP"]
 ==== C.FLDSP
 

src/insns/store_16bit_fp_dp.adoc

@@ -3,8 +3,6 @@
 ==== C.FSD
 See <<C.FSDSP>>.
 
-<<<
-
 [#C_FSDSP,reftext="C.FSDSP"]
 ==== C.FSDSP
 

src/insns/wavedrom/c-sp-load-store.adoc

@@ -9,6 +9,6 @@
   {bits: 5, name: 'imm',    type: 5, attr: ['5', 'offset[4:2|7:6]','offset[4:3|8:6]']},
   {bits: 5, name: 'rd',     type: 5, attr: ['5','dest!=0']},
   {bits: 1, name: 'imm',    type: 1, attr: ['1','[5]']},
-  {bits: 3, name: 'funct3', type: 3, attr: ['3', 'C.LWSP=010', 'C.LDSP=011']},
+  {bits: 3, name: 'funct3', type: 3, attr: ['3', 'C.LWSP=010', 'rv64: C.LDSP=011']},
 ], config: {bits: 16}}
 ....

src/insns/wavedrom/rv64_lui-auipc.adoc

@@ -3,7 +3,7 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',     attr: ['7', 'cap: AUIPCC=0010111', 'leg: AUIPC=0010111'], type: 8},
+  {bits: 7,  name: 'opcode',     attr: ['7', 'AUIPC=0010111'], type: 8},
   {bits: 5,  name: 'cd/rd',      attr: ['5', 'dest'], type: 2},
   {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]'], type: 3}
 ]}

src/instructions.adoc

@@ -69,7 +69,7 @@ include::insns/store_32bit_cap.adoc[]
 <<<
 === RV32I/E and RV64I/E Base Integer Instruction Sets
 
-include::insns/auipcc_32bit.adoc[]
+include::insns/auipc_32bit.adoc[]
 
 include::insns/condbr_32bit.adoc[]
 
@@ -260,8 +260,8 @@ See <<CM_JALT>>, <<CM_JT>>.
 If the access to the jump table succeeds, then the instructions execute as follows:
 
 * In capability mode
-** <<CM_JT>> executes as <<CJ>> or <<AUIPCC>>+<<CJR>>
-** <<CM_JALT>> executes as <<CJAL>> or <<AUIPCC>>+<<CJALR>>
+** <<CM_JT>> executes as <<CJ>> or <<AUIPC>>+<<CJR>>
+** <<CM_JALT>> executes as <<CJAL>> or <<AUIPC>>+<<CJALR>>
 * In legacy mode
 ** <<CM_JT>> executes as <<J>> or <<AUIPC>>+<<JR>>
 ** <<CM_JALT>> executes as <<JAL>> or <<AUIPC>>+<<JALR>>

src/riscv-integration.adoc

@@ -216,9 +216,8 @@ if the input register of the instruction holds a capability. The output is XLEN
 bits written to an *x* register; the tag and capability metadata of that
 register are zeroed.
 
-The add upper immediate to <<pcc>> instruction (<<AUIPCC>>) replaces the add upper
-immediate to *pc* instruction (<<AUIPC>>) at the same encoding. <<AUIPCC>> is used to
-build <<pcc>>-relative capabilities. <<AUIPCC>> forms a 32-bit offset from the 20-bit
+The add upper immediate to <<pcc>> instruction (<<AUIPC>>) is used to
+build <<pcc>>-relative capabilities. <<AUIPC>> forms a 32-bit offset from the 20-bit
 immediate and filling the lowest 12 bits with zeros. The <<pcc>> address is then
 incremented by the offset and a representability check is performed so the
 capability's tag is cleared if the new address is outside the <<pcc>>'s
@@ -1025,7 +1024,7 @@ Unlike machine and supervisor level CSRs, {cheri_base_ext_name} does not require
 ==== Program Counter Capability (pcc)
 
 The <<pcc>> is made visible in a CSR. This provides access to an
-<<infinite-cap>> capability while in debug mode without executing <<AUIPCC>>.
+<<infinite-cap>> capability while in debug mode without executing <<AUIPC>>.
 
 <<pcc>> resets to the <<infinite-cap>> capability with the address field set to the core boot address.
 

src/riscv-legacy-integration.adoc

@@ -254,7 +254,7 @@ endif::[]
 
 {cheri_legacy_ext_name} includes functions to disable most CHERI features. For
 example, executing in a privilege mode where the effective XLEN is less than
-XLENMAX. The following occurs when executing code in a privileged that has
+XLENMAX. The following occurs when executing code in a privileged mode that has
 CHERI disabled:
 
 * The CHERI instructions in xref:section_cap_instructions[xrefstyle=short] (and