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Continued renaming of instructions (#95)
This PR includes the following changes: - CSHxADD opcodes renamed to SHxADD - removed .cap suffix from prefetch.* and cbo.* - removed c prefix from Zcmp and Zcmt instructions See #80
1 parent 8bb2ccf commit 3dc7efc

23 files changed

+121
-248
lines changed

Diff for: ‎src/csv/CHERI_ISA.csv

+23-40
Original file line numberDiff line numberDiff line change
@@ -76,20 +76,13 @@
7676
"CSRRWI","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","CSR write - can also read/write a full capability through an address alias","CSR permission fault","","","","","","",""
7777
"CSRRSI","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","CSR set - can also read/write a full capability through an address alias","CSR permission fault","","","","","","",""
7878
"CSRRCI","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","CSR clear - can also read/write a full capability through an address alias","CSR permission fault","","","","","","",""
79-
"CBO.INVAL","✔","✔","✔","","","✔","","Legacy","","✔","","","","","","","","","","","","","2","MISC-MEM","","","","Cache block invalidate (implemented as clean), authorise with DDC","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
80-
"CBO.CLEAN","✔","✔","✔","","","✔","","Legacy","","✔","","","","","","","","","","","","","2","MISC-MEM","","","","Cache block clean, authorise with DDC","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
81-
"CBO.FLUSH","✔","✔","✔","","","✔","","Legacy","","✔","","","","","","","","","","","","","2","MISC-MEM","","","","Cache block flush, authorise with DDC","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
82-
"CBO.ZERO","✔","✔","✔","","","✔","","Legacy","","✔","","","","","","","","","","","","","2","MISC-MEM","","","","Cache block zero, authorise with DDC","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
83-
"CBO.INVAL.CAP","✔","✔","","","","","✔","Capability","","✔","","","","","","","","","","","","","2","MISC-MEM","","CBO.INVAL","CBO.INVAL","Cache block invalidate (implemented as clean), via cap","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
84-
"CBO.CLEAN.CAP","✔","✔","","","","","✔","Capability","","✔","","","","","","","","","","","","","2","MISC-MEM","","CBO.CLEAN","CBO.CLEAN","Cache block clean, via cap","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
85-
"CBO.FLUSH.CAP","✔","✔","","","","","✔","Capability","","✔","","","","","","","","","","","","","2","MISC-MEM","","CBO.FLUSH","CBO.FLUSH","Cache block flush, via cap","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
86-
"CBO.ZERO.CAP","✔","✔","","","","","✔","Capability","","✔","","","","","","","","","","","","","2","MISC-MEM","","CBO.ZERO","CBO.ZERO","Cache block zero, via cap","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
87-
"PREFETCH.R","✔","✔","✔","","","✔","","Legacy","","✔","","","","","","","","","","","","","","OP-IMM","","","","Prefetch instruction cache line, always valid","","","","","","","",""
88-
"PREFETCH.W","✔","✔","✔","","","✔","","Legacy","","✔","","","","","","","","","","","","","","OP-IMM","","","","Prefetch read-only data cache line, authorise with DDC","","","","","","","",""
89-
"PREFETCH.I","✔","✔","✔","","","✔","","Legacy","","✔","","","","","","","","","","","","","","OP-IMM","","","","Prefetch writeable data cache line, authorise with DDC","","","","","","","",""
90-
"PREFETCH.R.CAP","✔","✔","","","","","✔","Capability","","✔","","","","","","","","","","","","","","OP-IMM","","PREFETCH.R","PREFETCH.R","Prefetch read-only data cache line, via cap","","","","","","","",""
91-
"PREFETCH.W.CAP","✔","✔","","","","","✔","Capability","","✔","","","","","","","","","","","","","","OP-IMM","","PREFETCH.W","PREFETCH.W","Prefetch writeable data cache line, via cap","","","","","","","",""
92-
"PREFETCH.I.CAP","✔","✔","","","","","✔","Capability","","✔","","","","","","","","","","","","","","OP-IMM","","PREFETCH.I","PREFETCH.I","Prefetch instruction cache line, via cap","","","","","","","",""
79+
"CBO.INVAL","✔","✔","✔","","","✔","✔","Both","","✔","","","","","","","","","","","","","2","MISC-MEM","","","","Cache block invalidate (implemented as clean), authorise with DDC","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
80+
"CBO.CLEAN","✔","✔","✔","","","✔","✔","Both","","✔","","","","","","","","","","","","","2","MISC-MEM","","","","Cache block clean, authorise with DDC","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
81+
"CBO.FLUSH","✔","✔","✔","","","✔","✔","Both","","✔","","","","","","","","","","","","","2","MISC-MEM","","","","Cache block flush, authorise with DDC","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
82+
"CBO.ZERO","✔","✔","✔","","","✔","✔","Both","","✔","","","","","","","","","","","","","2","MISC-MEM","","","","Cache block zero, authorise with DDC","MODE<M AND menvcfg.CBIE[0]==0","MODE<S AND senvcfg.CBIE[0]==0","","","","","",""
83+
"PREFETCH.R","✔","✔","✔","","","✔","✔","Both","","✔","","","","","","","","","","","","","","OP-IMM","","","","Prefetch instruction cache line, always valid","","","","","","","",""
84+
"PREFETCH.W","✔","✔","✔","","","✔","✔","Both","","✔","","","","","","","","","","","","","","OP-IMM","","","","Prefetch read-only data cache line, authorise with DDC","","","","","","","",""
85+
"PREFETCH.I","✔","✔","✔","","","✔","✔","Both","","✔","","","","","","","","","","","","","","OP-IMM","","","","Prefetch writeable data cache line, authorise with DDC","","","","","","","",""
9386
"LR.C","✔","✔","","","","✔","✔","Both","✔","","","","","","","","","","","","","✔","","AMO","","","","Load reserve cap via int pointer, authorise with DDC","","","","","","","",""
9487
"LR.D","","","✔","","","✔","✔","Both","✔","","","","","","","","","","","","","","","AMO","","","","","","","","","","","",""
9588
"LR.W","","","✔","","","✔","✔","Both","✔","","","","","","","","","","","","","","","AMO","","","","","","","","","","","",""
@@ -121,29 +114,19 @@
121114
"FSW","✔","✔","","","","✔","✔","Both","","","","","","","","","","","✔","","","","","STORE-FP","","FSW","FSW","Store floating point word via cap","Xstatus.fs==0","","","","","","",""
122115
"FLD","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","✔","","","","LOAD-FP","","FLD","FLD","Load floating point double via cap","Xstatus.fs==0","","","","","","",""
123116
"FSD","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","✔","","","","STORE-FP","","FSD","FSD","Store floating point double via cap","Xstatus.fs==0","","","","","","",""
124-
"CM.PUSH","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Push integer stack frame","","","","","","","",""
125-
"CM.POP","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame","","","","","","","",""
126-
"CM.POPRET","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame and return","","","","","","","",""
127-
"CM.POPRETZ","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame and return zero","","","","","","","",""
128-
"CM.MVSA01","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Move two integer registers","","","","","","","",""
129-
"CM.MVA01S","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Move two integer registers","","","","","","","",""
130-
"CM.CPUSH","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.PUSH","CM.PUSH","Push capability stack frame","","","","","","","",""
131-
"CM.CPOP","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.POP","CM.POP","Pop capability stack frame","","","","","","","",""
132-
"CM.CPOPRET","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.POPRET","CM.POPRET","Pop capability stack frame and return","","","","","","","",""
133-
"CM.CPOPRETZ","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.POPRETZ","CM.POPRETZ","Pop capability stack frame and return zero","","","","","","","",""
134-
"CM.CMVSA01","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.MVSA01","CM.MVSA01","Move two capability registers","","","","","","","",""
135-
"CM.CMVA01S","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.MVA01S","CM.MVA01S","Move two capability registers","","","","","","","",""
136-
"CM.JALT","✔","✔","","","","✔","","Legacy","","","","","","","","","✔","","","","","","","C2","","","","Table jump and link","","","","","","","",""
137-
"CM.JT","✔","✔","","","","✔","","Legacy","","","","","","","","","✔","","","","","","","C2","","","","Table jump","","","","","","","",""
138-
"CM.CJALT","✔","✔","","","","","✔","Capability","","","","","","","","","✔","","","","","","","C2","","CM.JALT","CM.JALT","Table jump and link","","","","","","","",""
139-
"CM.CJT","✔","✔","","","","","✔","Capability","","","","","","","","","✔","","","","","","","C2","","CM.JT","CM.JT","Table jump","","","","","","","",""
140-
"CSH1ADD","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH1ADD","SH1ADD","shift and add, representability check on the result","","","","","","","",""
141-
"CSH1ADD.UW","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH1ADD.UW","SH1ADD.UW","shift and add, representability check on the result","","","","","","","",""
142-
"CSH2ADD","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH2ADD","SH2ADD","shift and add, representability check on the result","","","","","","","",""
143-
"CSH2ADD.UW","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH2ADD.UW","SH2ADD.UW","shift and add, representability check on the result","","","","","","","",""
144-
"CSH3ADD","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH3ADD","SH3ADD","shift and add, representability check on the result","","","","","","","",""
145-
"CSH3ADD.UW","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH3ADD.UW","SH3ADD.UW","shift and add, representability check on the result","","","","","","","",""
146-
"SH4ADD","","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","",""
147-
"SH4ADD.UW","","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","",""
148-
"CSH4ADD","","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","OP","","SH4ADD","SH4ADD","shift and add, representability check on the result","","","","","","","",""
149-
"CSH4ADD.UW","","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","OP","","SH4ADD.UW","SH4ADD.UW","shift and add, representability check on the result","","","","","","","",""
117+
"CM.PUSH","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Push integer stack frame","","","","","","","",""
118+
"CM.POP","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame","","","","","","","",""
119+
"CM.POPRET","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame and return","","","","","","","",""
120+
"CM.POPRETZ","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame and return zero","","","","","","","",""
121+
"CM.MVSA01","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Move two integer registers","","","","","","","",""
122+
"CM.MVA01S","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Move two integer registers","","","","","","","",""
123+
"CM.JALT","✔","✔","","","","✔","✔","Both","","","","","","","","","✔","","","","","","","C2","","","","Table jump and link","","","","","","","",""
124+
"CM.JT","✔","✔","","","","✔","✔","Both","","","","","","","","","✔","","","","","","","C2","","","","Table jump","","","","","","","",""
125+
"SH1ADD","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH1ADD","SH1ADD","shift and add, representability check on the result","","","","","","","",""
126+
"SH1ADD.UW","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH1ADD.UW","SH1ADD.UW","shift and add, representability check on the result","","","","","","","",""
127+
"SH2ADD","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH2ADD","SH2ADD","shift and add, representability check on the result","","","","","","","",""
128+
"SH2ADD.UW","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH2ADD.UW","SH2ADD.UW","shift and add, representability check on the result","","","","","","","",""
129+
"SH3ADD","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH3ADD","SH3ADD","shift and add, representability check on the result","","","","","","","",""
130+
"SH3ADD.UW","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH3ADD.UW","SH3ADD.UW","shift and add, representability check on the result","","","","","","","",""
131+
"SH4ADD","","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","",""
132+
"SH4ADD.UW","","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","",""

Diff for: ‎src/insns/cbo.clean.adoc

+6-11
Original file line numberDiff line numberDiff line change
@@ -3,16 +3,11 @@
33
[#CBO_CLEAN,reftext="CBO.CLEAN"]
44
==== CBO.CLEAN
55

6-
See <<CBO.CLEAN.CAP>>.
7-
8-
[#CBO_CLEAN_CAP,reftext="CBO.CLEAN.CAP"]
9-
==== CBO.CLEAN.CAP
10-
116
Synopsis::
127
Perform a clean operation on a cache block
138

149
Capability Mode Mnemonic::
15-
`cbo.clean.cap 0(cs1)`
10+
`cbo.clean 0(cs1)`
1611

1712
Legacy Mode Mnemonic::
1813
`cbo.clean 0(rs1)`
@@ -24,13 +19,13 @@ Encoding::
2419
{bits: 7, name: 'opcode', attr: ['7','MISC-MEM=0001111'], type: 8},
2520
{bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2},
2621
{bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8},
27-
{bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4},
28-
{bits: 12, name: 'funct12', attr: ['12','cap: CBO.CLEAN.CAP=00.001', 'leg: CBO.CLEAN=00.001'], type: 3},
22+
{bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4},
23+
{bits: 12, name: 'funct12', attr: ['12','CBO.CLEAN=00.001'], type: 3},
2924
]}
3025
....
3126

3227
Capability Mode Description::
33-
A CBO.CLEAN.CAP instruction performs a clean operation on the cache block
28+
A CBO.CLEAN instruction performs a clean operation on the cache block
3429
whose effective address is the base address specified in `cs1`. The authorising
3530
capability for this operation is `cs1`.
3631

@@ -42,10 +37,10 @@ capability for this operation is <<ddc>>.
4237
:cbo_clean_flush:
4338
include::cbo_exceptions.adoc[]
4439

45-
Prerequisites for CBO.CLEAN.CAP::
40+
Prerequisites for Capability Mode::
4641
Zicbom, {cheri_base_ext_name}
4742

48-
Prerequisites for CBO.CLEAN::
43+
Prerequisites for Legacy Mode::
4944
Zicbom, {cheri_legacy_ext_name}
5045

5146
Operation::

Diff for: ‎src/insns/cbo.flush.adoc

+5-10
Original file line numberDiff line numberDiff line change
@@ -3,16 +3,11 @@
33
[#CBO_FLUSH,reftext="CBO.FLUSH"]
44
==== CBO.FLUSH
55

6-
See <<CBO.FLUSH.CAP>>.
7-
8-
[#CBO_FLUSH_CAP,reftext="CBO.FLUSH.CAP"]
9-
==== CBO.FLUSH.CAP
10-
116
Synopsis::
127
Perform a flush operation on a cache block
138

149
Capability Mode Mnemonic::
15-
`cbo.flush.cap 0(cs1)`
10+
`cbo.flush 0(cs1)`
1611

1712
Legacy Mode Mnemonic::
1813
`cbo.flush 0(rs1)`
@@ -25,12 +20,12 @@ Encoding::
2520
{bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2},
2621
{bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8},
2722
{bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4},
28-
{bits: 12, name: 'funct12', attr: ['12','cap: CBO.FLUSH.CAP=00.0010', 'leg: CBO.FLUSH=00.0010'], type: 3},
23+
{bits: 12, name: 'funct12', attr: ['12','cap: CBO.FLUSH=00.0010'], type: 3},
2924
]}
3025
....
3126

3227
Capability Mode Description::
33-
A CBO.FLUSH.CAP instruction performs a flush operation on the cache block
28+
A CBO.FLUSH instruction performs a flush operation on the cache block
3429
whose effective address is the base address specified in `cs1`. The authorising
3530
capability for this operation is `cs1`.
3631

@@ -42,10 +37,10 @@ capability for this operation is <<ddc>>.
4237
:cbo_clean_flush:
4338
include::cbo_exceptions.adoc[]
4439

45-
Prerequisites for CBO.FLUSH.CAP::
40+
Prerequisites for Capability Mode::
4641
Zicbom, {cheri_base_ext_name}
4742

48-
Prerequisites for CBO.FLUSH::
43+
Prerequisites for Legacy Mode::
4944
Zicbom, {cheri_legacy_ext_name}
5045

5146
Operation::

Diff for: ‎src/insns/cbo.inval.adoc

+5-10
Original file line numberDiff line numberDiff line change
@@ -3,16 +3,11 @@
33
[#CBO_INVAL,reftext="CBO.INVAL"]
44
==== CBO.INVAL
55

6-
See <<CBO.INVAL.CAP>>.
7-
8-
[#CBO_INVAL_CAP,reftext="CBO.INVAL.CAP"]
9-
==== CBO.INVAL.CAP
10-
116
Synopsis::
127
Perform an invalidate operation on a cache block
138

149
Capability Mode Mnemonic::
15-
`cbo.inval.cap 0(cs1)`
10+
`cbo.inval 0(cs1)`
1611

1712
Legacy Mode Mnemonic::
1813
`cbo.inval 0(rs1)`
@@ -25,12 +20,12 @@ Encoding::
2520
{bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2},
2621
{bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8},
2722
{bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4},
28-
{bits: 12, name: 'funct12', attr: ['12','cap: CBO.INVAL.CAP=00.0000', 'leg: CBO.INVAL=00.0000'], type: 3},
23+
{bits: 12, name: 'funct12', attr: ['12','CBO.INVAL=00.0000'], type: 3},
2924
]}
3025
....
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Capability Mode Description::
33-
A CBO.INVAL.CAP instruction performs an invalidate operation on the cache block
28+
A CBO.INVAL instruction performs an invalidate operation on the cache block
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whose effective address is the base address specified in `cs1`. The authorising
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capability for this operation is `cs1`.
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@@ -42,10 +37,10 @@ authorising capability for this operation in <<ddc>>.
4237
:cbo_inval:
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include::cbo_exceptions.adoc[]
4439

45-
Prerequisites for CBO.INVAL.CAP::
40+
Prerequisites for Capability Mode::
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Zicbom, {cheri_base_ext_name}
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48-
Prerequisites for CBO.INVAL::
43+
Prerequisites for Legacy Mode::
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Zicbom, {cheri_legacy_ext_name}
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Operation::

Diff for: ‎src/insns/cbo.zero.adoc

+5-10
Original file line numberDiff line numberDiff line change
@@ -3,16 +3,11 @@
33
[#CBO_ZERO,reftext="CBO.ZERO"]
44
==== CBO.ZERO
55

6-
See <<CBO.ZERO.CAP>>.
7-
8-
[#CBO_ZERO_CAP,reftext="CBO.ZERO.CAP"]
9-
==== CBO.ZERO.CAP
10-
116
Synopsis::
127
Store zeros to the full set of bytes corresponding to a cache block
138

149
Capability Mode Mnemonic::
15-
`cbo.zero.cap 0(cs1)`
10+
`cbo.zero 0(cs1)`
1611

1712
Legacy Mode Mnemonic::
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`cbo.zero 0(rs1)`
@@ -25,12 +20,12 @@ Encoding::
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{bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2},
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{bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8},
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{bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4},
28-
{bits: 12, name: 'funct12', attr: ['12','cap: CBO.ZERO.CAP=00.0100', 'leg: CBO.ZERO=00.0100'], type: 3},
23+
{bits: 12, name: 'funct12', attr: ['12','CBO.ZERO=00.0100'], type: 3},
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]}
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....
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3227
Capability Mode Description::
33-
A `cbo.zero.cap` instruction performs stores of zeros to the full set of bytes
28+
A `cbo.zero` instruction performs stores of zeros to the full set of bytes
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corresponding to the cache block whose effective address is the base address
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specified in `cs1`. An implementation may or may not update the entire set of
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bytes atomically although each individual write must atomically clear the tag
@@ -47,10 +42,10 @@ for this operation is <<ddc>>.
4742

4843
include::store_exceptions.adoc[]
4944

50-
Prerequisites for CBO.ZERO.CAP::
45+
Prerequisites for Capability Mode::
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Zicboz, {cheri_base_ext_name}
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53-
Prerequisites for CBO.ZERO::
48+
Prerequisites for Legacy Mode::
5449
Zicboz, {cheri_legacy_ext_name}
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Operation::

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