Did spell checking of all instructions

src/insns/acperm_32bit.adoc

@@ -66,7 +66,7 @@ The rules from <<acperm_rules>> must be followed when removing permissions.
 
 ^1^ All the listed permissions in the set are either minimum or maximum.
 
-The behaviour of currently illegal combinations from <<acperm_rules>> is to clear the permission if invalid (or in the case of <<sl_perm>> set it to 0 (_local_)).
+The behavior of currently illegal combinations from <<acperm_rules>> is to clear the permission if invalid (or in the case of <<sl_perm>> set it to 0 (_local_)).
 
 * For RV64 all such combinations may be redefined by future extensions.
 * The RV32 only rules are added because they remove combinations which do not meet the encoding requirements for <<cap_perms_encoding32>>, or

src/insns/amo_32bit.adoc

@@ -29,12 +29,12 @@ Encoding::
 include::wavedrom/amo.adoc[]
 
 {cheri_cap_mode_name} Description::
-Standard atomic instructions, authorised by the capability in `cs1`.
+Standard atomic instructions, authorized by the capability in `cs1`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
-Standard atomic instructions, authorised by the capability in <<ddc>>.
+Standard atomic instructions, authorized by the capability in <<ddc>>.
 
 include::atomic_exceptions.adoc[]
 

src/insns/amoswap_32bit_cap.adoc

@@ -16,12 +16,12 @@ Encoding::
 include::wavedrom/amoswap_cap.adoc[]
 
 {cheri_cap_mode_name} Description::
-Atomic swap of capability type, authorised by the capability in `cs1`.
+Atomic swap of capability type, authorized by the capability in `cs1`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
-Atomic swap of capability type, authorised by the capability in <<ddc>>.
+Atomic swap of capability type, authorized by the capability in <<ddc>>.
 
 :cap_atomic:
 

src/insns/atomic_exceptions.adoc

@@ -2,7 +2,7 @@ Permissions::
 ifdef::cap_atomic[]
 Requires the authorizing capability to be tagged and not sealed.
 +
-Requires <<r_perm>> and <<w_perm>> in the authorising capability.
+Requires <<r_perm>> and <<w_perm>> in the authorizing capability.
 +
 If <<c_perm>> is not granted then store the memory tag as zero, and load `cd.tag` as zero.
 +
@@ -14,7 +14,7 @@ If `cd` is not sealed, this implicit <<ACPERM>> also clears <<el_perm>> to obtai
 The stored tag is also set to zero if the authorizing capability does not have <<sl_perm>> set but the stored data has a <<section_cap_level>> of 0 (see <<SC>>).
 endif::[]
 ifndef::cap_atomic[]
-Requires <<r_perm>> and <<w_perm>> in the authorising capability.
+Requires <<r_perm>> and <<w_perm>> in the authorizing capability.
 endif::[]
 +
 Requires all bytes of the access to be in capability bounds.

src/insns/cbo.clean.adoc

@@ -26,12 +26,12 @@ Encoding::
 
 {cheri_cap_mode_name} Description::
 A CBO.CLEAN instruction performs a clean operation on the cache block
-whose effective address is the base address specified in `cs1`. The authorising
+whose effective address is the base address specified in `cs1`. The authorizing
 capability for this operation is `cs1`.
 
 {cheri_int_mode_name} Description::
 A CBO.CLEAN instruction performs a clean operation on the cache block whose
-effective address is the base address specified in `rs1`. The authorising
+effective address is the base address specified in `rs1`. The authorizing
 capability for this operation is <<ddc>>.
 
 :cbo_clean_flush:

src/insns/cbo.flush.adoc

@@ -26,12 +26,12 @@ Encoding::
 
 {cheri_cap_mode_name} Description::
 A CBO.FLUSH instruction performs a flush operation on the cache block
-whose effective address is the base address specified in `cs1`. The authorising
+whose effective address is the base address specified in `cs1`. The authorizing
 capability for this operation is `cs1`.
 
 {cheri_int_mode_name} Description::
 A CBO.FLUSH instruction performs a flush operation on the cache block whose
-effective address is the base address specified in `rs1`. The authorising
+effective address is the base address specified in `rs1`. The authorizing
 capability for this operation is <<ddc>>.
 
 :cbo_clean_flush:

src/insns/cbo.inval.adoc

@@ -26,13 +26,13 @@ Encoding::
 
 {cheri_cap_mode_name} Description::
 A CBO.INVAL instruction performs an invalidate operation on the cache block
-whose effective address is the base address specified in `cs1`. The authorising
+whose effective address is the base address specified in `cs1`. The authorizing
 capability for this operation is `cs1`.
 
 {cheri_int_mode_name} Description::
 A CBO.INVAL instruction performs an invalidate operation on the cache block
 whose effective address is the base address specified in `rs1`. The
-authorising capability for this operation in <<ddc>>.
+authorizing capability for this operation in <<ddc>>.
 
 :cbo_inval:
 include::cbo_exceptions.adoc[]

src/insns/cbo.zero.adoc

@@ -29,15 +29,15 @@ A `cbo.zero` instruction performs stores of zeros to the full set of bytes
 corresponding to the cache block whose effective address is the base address
 specified in `cs1`. An implementation may or may not update the entire set of
 bytes atomically although each individual write must atomically clear the tag
-bit of the corresponding aligned CLEN-bit location. The authorising capability
+bit of the corresponding aligned CLEN-bit location. The authorizing capability
 for this operation is `cs1`.
 
 {cheri_int_mode_name} Description::
 A `cbo.zero` instruction performs stores of zeros to the full set of bytes
 corresponding to the cache block whose effective address is the base address
 specified in `cs1`. An implementation may or may not update the entire set of
 bytes atomically although each individual write must atomically clear the tag
-bit of the corresponding aligned CLEN-bit location. The authorising capability
+bit of the corresponding aligned CLEN-bit location. The authorizing capability
 for this operation is <<ddc>>.
 
 include::store_exceptions.adoc[]

src/insns/cbo_exceptions.adoc

@@ -1,5 +1,5 @@
 Exceptions::
-CHERI fault exceptions occur when the authorising capability fails one of the checks
+CHERI fault exceptions occur when the authorizing capability fails one of the checks
 listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
 <<stval2>> TYPE field and the corresponding code is written to CAUSE.
 +

src/insns/hypv-virt-load-cap.adoc

@@ -19,15 +19,15 @@ include::wavedrom/hypv-virt-load-cap.adoc[]
 Load a CLEN+1 bit value from memory as though V=1; i.e., with the address
 translation and protection, and endianness, that apply to memory accesses in
 either VS-mode or VU-mode. The effective address is the address of `cs1`. The
-authorising capability for the operation is `cs1`. A copy of the loaded value
+authorizing capability for the operation is `cs1`. A copy of the loaded value
 is written to `cd`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load a CLEN+1 bit value from memory as though V=1; i.e., with the address
 translation and protection, and endianness, that apply to memory accesses in
-either VS-mode and VU-mode. The effective address is `rs1`. The authorising
+either VS-mode and VU-mode. The effective address is `rs1`. The authorizing
 capability for the operation is <<ddc>>. A copy of the loaded value is written
 to `cd`.
 

src/insns/hypv-virt-load.adoc

@@ -66,7 +66,7 @@ include::wavedrom/hypv-virt-load.adoc[]
 {cheri_cap_mode_name} Description::
 Performs a load as though V=1; i.e., with the address translation and
 protection, and endianness, that apply to memory accesses in either VS-mode or
-VU-mode. The effective address is the address of `cs1`. The authorising
+VU-mode. The effective address is the address of `cs1`. The authorizing
 capability for the operation is `cs1`. A copy of the loaded value is written to
 `rd`.
 +
@@ -75,7 +75,7 @@ include::load_store_c0.adoc[]
 {cheri_int_mode_name} Description::
 Performs a load as though V=1; i.e., with the address translation and
 protection, and endianness, that apply to memory accesses in either VS-mode or
-VU-mode. The effective address is the is `rs1`. The authorising capability for
+VU-mode. The effective address is the is `rs1`. The authorizing capability for
 the operation is <<ddc>>. A copy of the loaded value is written to `rd`.
 
 include::load_exceptions.adoc[]

src/insns/hypv-virt-loadx.adoc

@@ -27,7 +27,7 @@ Performs a load with the *execute* permission taking the place of *read*
 permission during address translation and as though V=1; i.e., with the address
 translation and protection, and endianness, that apply to memory access in
 either VS-mode or VU-mode. The effective address is the address of `cs1`. The
-authorising capability for the operation is `cs1`. A copy of the loaded value
+authorizing capability for the operation is `cs1`. A copy of the loaded value
 is written to `rd`.
 +
 include::load_store_c0.adoc[]
@@ -36,12 +36,12 @@ include::load_store_c0.adoc[]
 Performs a load with the *execute* permission taking the place of *read*
 permission during address translation and as though V=1; i.e., with the address
 translation and protection, and endianness, that apply to memory access in
-either VS-mode or VU-mode. The effective address is `rs1`. The authorising
+either VS-mode or VU-mode. The effective address is `rs1`. The authorizing
 capability for the operation is <<ddc>>. A copy of the loaded value is written
 to `rd`.
 
 Exceptions::
-CHERI fault exceptions occur when the authorising capability fails one of the checks
+CHERI fault exceptions occur when the authorizing capability fails one of the checks
 listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
 <<stval2>> TYPE field and the corresponding code is written to CAUSE.
 +

src/insns/hypv-virt-store-cap.adoc

@@ -19,15 +19,15 @@ include::wavedrom/hypv-virt-store-cap.adoc[]
 Store a CLEN+1 bit value in `cs2` to memory as though V=1; i.e., with the
 address translation and protection, and endianness, that apply to memory
 accesses in either VS-mode or VU-mode. The effective address is the address of
-`cs1`. The authorising capability for the operation is `cs1`.
+`cs1`. The authorizing capability for the operation is `cs1`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store a CLEN+1 bit value in `cs2` to memory as though V=1; i.e., with the
 address translation and protection, and endianness, that apply to memory
 accesses in either VS-mode or VU-mode. The effective address is the `rs1`. The
-authorising capability for the operation is <<ddc>>.
+authorizing capability for the operation is <<ddc>>.
 
 include::store_tag_perms.adoc[]
 

src/insns/hypv-virt-store.adoc

@@ -51,7 +51,7 @@ include::wavedrom/hypv-virt-store.adoc[]
 {cheri_cap_mode_name} Description::
 Performs a store as though V=1; i.e., with the address translation and
 protection, and endianness, that apply to memory accesses in either VS-mode or
-VU-mode. The effective address is the address of `cs1`. The authorising
+VU-mode. The effective address is the address of `cs1`. The authorizing
 capability for the operation is `cs1`. A copy of `rs2` is written to memory at
 the location indicated by the effective address and the tag bit of each block
 of memory naturally aligned to CLEN/8 is cleared.
@@ -61,7 +61,7 @@ include::load_store_c0.adoc[]
 {cheri_int_mode_name} Description::
 Performs a store as though V=1; i.e., with address translation and protection,
 and endianness, that apply to memory accesses in either VS-mode or VU-mode. The
-effective address is `rs1`. The authorising capability for the operation is
+effective address is `rs1`. The authorizing capability for the operation is
 <<ddc>>. A copy of `rs2` is written to memory at the location indicated by the
 effective address and the tag bit of each block of memory naturally aligned to
 CLEN/8 is cleared.

src/insns/load_16bit.adoc

@@ -44,10 +44,10 @@ Encoding::
 include::wavedrom/reg-based-ldnstr.adoc[]
 
 {cheri_cap_mode_name} Description::
-Standard load instructions, authorised by the capability in `cs1`.
+Standard load instructions, authorized by the capability in `cs1`.
 
 {cheri_int_mode_name} Description::
-Standard load instructions, authorised by the capability in <<ddc>>.
+Standard load instructions, authorized by the capability in <<ddc>>.
 
 include::load_exceptions.adoc[]
 

src/insns/load_16bit_Zcb.adoc

@@ -41,10 +41,10 @@ Encoding::
 include::wavedrom/reg-based-ldnstr-Zcb.adoc[]
 
 {cheri_cap_mode_name} Description::
-Subword load instructions, authorised by the capability in `cs1`.
+Subword load instructions, authorized by the capability in `cs1`.
 
 {cheri_int_mode_name} Description::
-Subword load instructions, authorised by the capability in <<ddc>>.
+Subword load instructions, authorized by the capability in <<ddc>>.
 
 include::load_exceptions.adoc[]
 

src/insns/load_16bit_fp_dp.adoc

@@ -27,7 +27,7 @@ include::wavedrom/c-sp-load-css-dp.adoc[]
 include::wavedrom/c-sp-load-css-dp-sprel.adoc[]
 
 {cheri_int_mode_name} Description::
-Standard floating point stack pointer relative load instructions, authorised by the capability in <<ddc>>.
+Standard floating point stack pointer relative load instructions, authorized by the capability in <<ddc>>.
 
 NOTE: These instructions are available in RV64 {cheri_int_mode_name} only.
 In RV64 {cheri_cap_mode_name} they are remapped to <<C.LC>>/<<C.LCSP>>.

src/insns/load_16bit_fp_sp.adoc

@@ -22,7 +22,7 @@ include::wavedrom/c-sp-load-css-fp.adoc[]
 include::wavedrom/c-sp-load-css-fp-sprel.adoc[]
 
 {cheri_int_mode_name} Description::
-Standard floating point load instructions, authorised by the capability in <<ddc>>.
+Standard floating point load instructions, authorized by the capability in <<ddc>>.
 
 NOTE: These instructions are available in RV32 {cheri_int_mode_name} only.
 In {cheri_cap_mode_name} they are remapped to <<C.LC>>/<<C.LCSP>>.

src/insns/load_16bit_sprel.adoc

@@ -41,10 +41,10 @@ Encoding::
 include::wavedrom/c-sp-load-store.adoc[]
 
 {cheri_cap_mode_name} Description::
-Standard stack pointer relative load instructions, authorised by the capability in `csp`.
+Standard stack pointer relative load instructions, authorized by the capability in `csp`.
 
 {cheri_int_mode_name} Description::
-Standard stack pointer relative load instructions, authorised by the capability in <<ddc>>.
+Standard stack pointer relative load instructions, authorized by the capability in <<ddc>>.
 
 include::load_exceptions.adoc[]
 

src/insns/load_32bit.adoc

@@ -66,15 +66,15 @@ include::wavedrom/load.adoc[]
 {cheri_cap_mode_name} Description::
 Load integer data of the indicated size (byte, halfword, word, double-word)
 from memory. The effective address of the load is obtained by adding the
-sign-extended 12-bit offset to the address of `cs1`. The authorising capability
+sign-extended 12-bit offset to the address of `cs1`. The authorizing capability
 for the operation is `cs1`. A copy of the loaded value is written to `rd`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load integer data of the indicated size (byte, halfword, word, double-word)
 from memory. The effective address of the load is obtained by adding the
-sign-extended 12-bit offset to `rs1`. The authorising capability for the
+sign-extended 12-bit offset to `rs1`. The authorizing capability for the
 operation is <<ddc>>. A copy of the loaded value is written to `rd`.
 
 include::load_exceptions.adoc[]

src/insns/load_32bit_cap.adoc

@@ -26,7 +26,7 @@ include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Loads a CLEN+1 bit value from memory and writes it to `cd`. The capability
-authorising the operation is <<ddc>>. The effective address of the memory
+authorizing the operation is <<ddc>>. The effective address of the memory
 access is obtained by adding `rs1` to the sign-extended 12-bit offset.
 
 include::load_tag_perms.adoc[]

src/insns/load_32bit_fp.adoc

@@ -30,12 +30,12 @@ Encoding::
 include::wavedrom/fpload.adoc[]
 
 {cheri_cap_mode_name} Description::
-Standard floating point load instructions, authorised by the capability in `cs1`.
+Standard floating point load instructions, authorized by the capability in `cs1`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
-Standard floating point load instructions, authorised by the capability in <<ddc>>.
+Standard floating point load instructions, authorized by the capability in <<ddc>>.
 
 :!cap_load:
 include::load_exceptions.adoc[]

src/insns/load_cap_cap_description.adoc

@@ -1,2 +1,2 @@
 {cheri_cap_mode_name} Description::
-Load capability instruction, authorised by the capability in `cs1`. Take a load address misaligned exception if not naturally aligned.
+Load capability instruction, authorized by the capability in `cs1`. Take a load address misaligned exception if not naturally aligned.

src/insns/load_cap_int_description.adoc

@@ -1,2 +1,2 @@
 {cheri_int_mode_name} Description::
-Load capability instruction, authorised by the capability in <<ddc>>. Take a load address misaligned exception if not naturally aligned.
+Load capability instruction, authorized by the capability in <<ddc>>. Take a load address misaligned exception if not naturally aligned.

src/insns/load_exceptions.adoc

@@ -8,7 +8,7 @@ Misaligned address fault exception when the effective address is not aligned
 to CLEN/8.
 +
 endif::[]
-CHERI fault exceptions occur when the authorising capability fails one of the checks
+CHERI fault exceptions occur when the authorizing capability fails one of the checks
 listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
 <<stval2>> TYPE field and the corresponding code is written to CAUSE.
 +

src/insns/load_res_32bit.adoc

@@ -36,12 +36,12 @@ Encoding::
 include::wavedrom/load_res.adoc[]
 
 {cheri_cap_mode_name} Description::
-Load reserved instructions, authorised by the capability in `cs1`.
+Load reserved instructions, authorized by the capability in `cs1`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
-Load reserved instructions, authorised by the capability in <<ddc>>.
+Load reserved instructions, authorized by the capability in <<ddc>>.
 
 :load_res:
 

src/insns/load_res_cap_32bit.adoc

@@ -16,13 +16,13 @@ Encoding::
 include::wavedrom/load_res_cap.adoc[]
 
 {cheri_cap_mode_name} Description::
-Load reserved instructions, authorised by the capability in `cs1`.
+Load reserved instructions, authorized by the capability in `cs1`.
  All misaligned load reservations cause a load address misaligned exception to allow software emulation (Zam extension, see cite:[riscv-unpriv-spec]).
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
-Load reserved instructions, authorised by the capability in <<ddc>>.
+Load reserved instructions, authorized by the capability in <<ddc>>.
  All misaligned load reservations cause a load address misaligned exception to allow software emulation (Zam extension, see cite:[riscv-unpriv-spec]).
 
 include::load_tag_perms.adoc[]

src/insns/prefetch.i.adoc

@@ -31,7 +31,7 @@ A PREFETCH.I instruction indicates to hardware that the cache block whose
 effective address is the sum of the base address specified in `cs1` and the
 sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is
 likely to be accessed by an instruction fetch in the near future. The encoding
-is only valid if imm[4:0]=0. The authorising capability for this operation is
+is only valid if imm[4:0]=0. The authorizing capability for this operation is
 `cs1`. This instruction does not throw any exceptions. However, following
 xref:CHERI_SPEC[xrefstyle=short], this instruction does not perform a prefetch
 if it is not authorized by `cs1`.
@@ -41,7 +41,7 @@ A PREFETCH.I instruction indicates to hardware that the cache block whose
 effective address is the sum of the base address specified in `rs1` and the
 sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is
 likely to be accessed by an instruction fetch in the near future. The encoding
-is only valid if imm[4:0]=0. The authorising capability for this operation is
+is only valid if imm[4:0]=0. The authorizing capability for this operation is
 <<pcc>>.
 
 :prefetch_insn: PREFETCH.I