remove C prefix from capability mode load/store/atomics

src/insns/amo_32bit.adoc

@@ -1,16 +1,4 @@
 <<<
-//[#insns-amo-32bit,reftext="Atomic (CAMO<OP>.W, CAMO<OP>.D, AMO<OP>.W, AMO<OP>.D), 32-bit encodings"]
-
-
-[#CAMOOPW,reftext="CAMO<OP>.W"]
-==== CAMO<OP>.W
-
-See <<AMOOPD>>.
-
-[#CAMOOPD,reftext="CAMO<OP>.D"]
-==== CAMO<OP>.D
-
-See <<AMOOPD>>.
 
 [#AMOOPW,reftext="AMO<OP>.W"]
 ==== AMO<OP>.W
@@ -20,16 +8,16 @@ See <<AMOOPD>>.
 <<<
 
 [#AMOOPD,reftext="AMO<OP>.D"]
-==== CAMO<OP>.W
+==== AMO<OP>.W
 
 Synopsis::
-Atomic Operations (CAMO<OP>.W, CAMO<OP>.D, AMO<OP>.W, AMO<OP>.D), 32-bit encodings
+Atomic Operations (AMO<OP>.W, AMO<OP>.D), 32-bit encodings
 
 Capability Mode Mnemonics (RV64)::
-`camo<op>.[w|d], offset(cs1)`
+`amo<op>.[w|d], offset(cs1)`
 
 Capability Mode Mnemonics (RV32)::
-`camo<op>.w, offset(cs1)`
+`amo<op>.w, offset(cs1)`
 
 Legacy Mode Mnemonics (RV64)::
 `amo<op>.[w|d], offset(rs1)`
@@ -48,11 +36,11 @@ Standard atomic instructions, authorised by the capability in <<ddc>>.
 
 include::atomic_exceptions.adoc[]
 
-Prerequisites for CAMO<OP>.W, CAMO<OP>.D::
-{cheri_base_ext_name}
+Prerequisites for AMO<OP>.W, AMO<OP>.D::
+{cheri_base_ext_name}, and A, or +
+{cheri_legacy_ext_name}, and A
 
 Prerequisites for AMO<OP>.W, AMO<OP>.D::
-{cheri_legacy_ext_name}
 
 Capability Mode Operation::
 [source,SAIL,subs="verbatim,quotes"]

src/insns/amoswap_32bit_cap.adoc

@@ -3,20 +3,15 @@
 [#AMOSWAP_C,reftext="AMOSWAP.C"]
 ==== AMOSWAP.C
 
-See <<CAMOSWAP.C>>.
-
-[#CAMOSWAP_C,reftext="CAMOSWAP.C"]
-==== CAMOSWAP.C
-
 NOTE: The RV64 encoding is intended to also allocate the encoding for AMOSWAP.Q for RV128.
 
 Synopsis::
-Atomic Operations (CAMOSWAP.C, AMOSWAP.C), 32-bit encodings
+Atomic Operation (AMOSWAP.C), 32-bit encoding
 
 include::xlen_variable_warning.adoc[]
 
 Capability Mode Mnemonics::
-`camoswap.c, offset(cs1)`
+`amoswap.c, offset(cs1)`
 
 Legacy Mode Mnemonics::
 `amoswap.c, offset(rs1)`
@@ -34,11 +29,9 @@ Atomic swap of capability type, authorised by the capability in <<ddc>>.
 
 include::atomic_exceptions.adoc[]
 
-Prerequisites for CAMOSWAP.C::
-{cheri_base_ext_name}
-
 Prerequisites for AMOSWAP.C::
-{cheri_legacy_ext_name}
+{cheri_base_ext_name}, and A, or +
+{cheri_legacy_ext_name}, and A
 
 Operation::
 +

src/insns/load_16bit.adoc

@@ -1,13 +1,4 @@
 <<<
-//[#insns-load-16bit,reftext="Load (C.CLD, C.CLW, C.LD, C.LW), 16-bit encodings"]
-
-[#C_CLD,reftext="C.CLD"]
-==== C.CLD
-See <<C_LW>>.
-
-[#C_CLW,reftext="C.CLW"]
-==== C.CLW
-See <<C_LW>>.
 
 [#C_LD,reftext="C.LD"]
 ==== C.LD
@@ -19,13 +10,13 @@ See <<C_LW>>.
 ==== C.LW
 
 Synopsis::
-Load (C.CLD, C.CLW, C.LD, C.LW), 16-bit encodings
+Load (C.LD, C.LW), 16-bit encodings
 
 Capability Mode Mnemonics (RV64)::
-`c.cld/c.clw rd', offset(cs1')`
+`c.ld/c.lw rd', offset(cs1')`
 
 Capability Mode Expansions (RV64)::
-`cld/clw rd', offset(cs1')`
+`ld/lw rd', offset(cs1')`
 
 Legacy Mode Mnemonics (RV64)::
 `c.ld/c.lw rd', offset(rs1')`
@@ -34,10 +25,10 @@ Legacy Mode Expansions (RV64)::
 `ld/lw rd', offset(rs1')`
 
 Capability Mode Mnemonics (RV32)::
-`c.clw rd', offset(cs1')`
+`c.lw rd', offset(cs1')`
 
 Capability Mode Expansions (RV32)::
-`clw rd', offset(cs1')`
+`lw rd', offset(cs1')`
 
 Legacy Mode Mnemonics (RV32)::
 `c.lw rd', offset(rs1')`
@@ -56,17 +47,13 @@ Standard load instructions, authorised by the capability in <<ddc>>.
 
 include::load_exceptions.adoc[]
 
-Prerequisites C.CLD::
-RV64, and {c_cheri_base_ext_names}
-
-Prerequisites C.CLW::
-{c_cheri_base_ext_names}
-
 Prerequisites C.LD::
+RV64, and {c_cheri_base_ext_names}, or +
 RV64, {c_cheri_legacy_ext_names}
 
 Prerequisites C.LW::
+{c_cheri_base_ext_names}, or +
 {c_cheri_legacy_ext_names}
 
 Operation (after expansion to 32-bit encodings)::
- See <<CLD>>, <<CLW>>, <<LD>>, <<LW>>
+ See <<LD>>, <<LW>>

src/insns/load_16bit_Zcb.adoc

@@ -1,19 +1,4 @@
 <<<
-//[#insns-load-16bit-Zcb,reftext="Load (C.CLH, C.CLHU, C.CLBU, C.LH, C.LHU, C.LBU), 16-bit encodings"]
-
-
-
-[#C_CLH,reftext="C.CLH"]
-==== C.CLH
-See <<C.LBU>>.
-
-[#C_CLHU,reftext="C.CLHU"]
-==== C.CLHU
-See <<C.LBU>>.
-
-[#C_CLBU,reftext="C.CLBU"]
-==== C.CLBU
-See <<C.LBU>>.
 
 [#C_LH,reftext="C.LH"]
 ==== C.LH
@@ -29,13 +14,13 @@ See <<C.LBU>>.
 ==== C.LBU
 
 Synopsis::
-Load (C.CLH, C.CLHU, C.CLBU, C.LH, C.LHU, C.LBU), 16-bit encodings
+Load (C.LH, C.LHU, C.LBU), 16-bit encodings
 
 Capability Mode Mnemonics::
-`c.clh/c.clhu/c.clbu rd', offset(cs1')`
+`c.lh/c.lhu/c.lbu rd', offset(cs1')`
 
 Capability Mode Expansions::
-`clh/clhu/clbu rd, offset(cs1)`
+`lh/lhu/lbu rd, offset(cs1)`
 
 Legacy Mode Mnemonics::
 `c.lh/c.lhu/c.lbu rd', offset(rs1')`
@@ -55,11 +40,9 @@ Subword load instructions, authorised by the capability in <<ddc>>.
 
 include::load_exceptions.adoc[]
 
-Prerequisites C.CLH, C.CLHU, C.CLBU::
-{c_cheri_base_ext_names}, and Zcb
-
 Prerequisites C.LH, C.LHU, C.LBU::
+{c_cheri_base_ext_names}, and Zcb, or +
 {c_cheri_legacy_ext_names}, and Zcb
 
 Operation (after expansion to 32-bit encodings)::
- See <<C.CLH>>, <<CLHU>>, <<CLBU>>, <<LH>>, <<LHU>>, <<LBU>>
+ See <<LHU>>, <<LH>>, <<LBU>>

src/insns/load_16bit_cap_sprel.adoc

@@ -1,22 +1,21 @@
 <<<
-//[#insns-load-16bit-cap-sprel,reftext="Load capability (C.CLC, C.CLCSP), 16-bit encodings"]
 
-[#C_CLC,reftext="C.CLC"]
-==== C.CLC
+[#C_LC,reftext="C.LC"]
+==== C.LC
 
-see <<C_CLCSP>>.
+see <<C_LCSP>>.
 
-[#C_CLCSP,reftext="C.CLCSP"]
-==== C.CLCSP
+[#C_LCSP,reftext="C.LCSP"]
+==== C.LCSP
 
 Synopsis::
-Capability loads (C.CLC, C.CLCSP), 16-bit encodings
+Capability loads (C.LC, C.LCSP), 16-bit encodings
 
 Capability Mode Mnemonics::
-`c.clc cd', offset(cs1'/csp)`
+`c.lc cd', offset(cs1'/csp)`
 
 Capability Mode Expansions::
-`clc cd', offset(cs1'/csp)`
+`lc cd', offset(cs1'/csp)`
 
 Encoding::
 include::wavedrom/c-sp-load-cap.adoc[]
@@ -32,4 +31,4 @@ Prerequisites::
 {c_cheri_base_ext_names}
 
 Operation (after expansion to 32-bit encodings)::
- See <<CLC>>
+ See <<LC>>

src/insns/load_16bit_fp_dp.adoc

@@ -1,63 +1,45 @@
 <<<
-//[#insns-load-16bit-fp-sprel,reftext="Load (C.CFLD, C.FLD, C.CFLDSP, C.FLDSP), 16-bit encodings"]
-
-[#C_CFLD,reftext="C.CFLD"]
-==== C.CFLD
-
-See <<C.FLDSP>>.
-
 [#C_FLD,reftext="C.FLD"]
 ==== C.FLD
 
 See <<C.FLDSP>>.
 
-[#C_CFLDSP,reftext="C.CFLDSP"]
-==== C.CFLDSP
-
-See <<C.FLDSP>>.
-
 <<<
 
 [#C_FLDSP,reftext="C.FLDSP"]
 ==== C.FLDSP
 
 Synopsis::
-Double precision floating point loads (C.CFLD, C.FLD, C.CFLDSP, C.FLDSP), 16-bit encodings
+Double precision floating point loads (C.FLD, C.FLDSP), 16-bit encodings
 
 Capability Mode Mnemonics (RV32)::
-`c.cfld frd', offset(cs1'/csp)`
+`c.fld frd', offset(cs1'/csp)`
 
 Capability Mode Expansions (RV32)::
-`cfld frd', offset(csp)`
+`fld frd', offset(csp)`
 
-Legacy Mode Mnemonics (RV32)::
+Legacy Mode Mnemonics::
 `c.fld fs2, offset(rs1'/sp)`
 
-Legacy Mode Expansions (RV32)::
-`fld fs2, offset(rs1'/sp)`
-
-Legacy Mode Mnemonics (RV64)::
-`c.fld fs2, offset(rs1'/sp)`
-
-Legacy Mode Expansion (RV64)::
+Legacy Mode Expansions::
 `fld fs2, offset(rs1'/sp)`
 
 Encoding::
 include::wavedrom/c-sp-load-css-dp.adoc[]
 include::wavedrom/c-sp-load-css-dp-sprel.adoc[]
 
 Legacy Mode Description::
-Standard floating point stack pointer relative load instructions, authorised by the capability in <<ddc>>. Note that these instructions are not available in Capability Mode, as they have been remapped to <<C.CLC>>, <<C.CLCSP>>.
+Standard floating point stack pointer relative load instructions, authorised by the capability in <<ddc>>. Note that these instructions are not available in Capability Mode, as they have been remapped to <<C.LC>>, <<C.LCSP>>.
 
 include::load_exceptions.adoc[]
 
-Prerequisites for C.CFLD, C.CFLDSP (RV32 only)::
+Prerequisites for C.FLD, C.FLDSP (RV32 only)::
 {cheri_base_ext_name}, C and D; or +
 {cheri_base_ext_name}, Zca and Zcd
 
 Prerequisites for C.FLD, C.FLDSP::
-{cheri_base_ext_name}, C and D; or +
-{cheri_base_ext_name}, Zca and Zcd
+{cheri_legacy_ext_name}, C and D; or +
+{cheri_legacy_ext_name}, Zca and Zcd
 
 Operation (after expansion to 32-bit encodings)::
  See <<FLD>>

src/insns/load_16bit_fp_sp.adoc

@@ -22,7 +22,7 @@ include::wavedrom/c-sp-load-css-fp.adoc[]
 include::wavedrom/c-sp-load-css-fp-sprel.adoc[]
 
 Legacy Mode Description::
-Standard floating point load instructions, authorised by the capability in <<ddc>>. Note that these instructions are not available in Capability Mode, as they have been remapped to <<C.CLC>>, <<C.CLCSP>>.
+Standard floating point load instructions, authorised by the capability in <<ddc>>. Note that these instructions are not available in Capability Mode, as they have been remapped to <<C.LC>>, <<C.LCSP>>.
 
 include::load_exceptions.adoc[]
 

src/insns/load_16bit_sprel.adoc

@@ -1,15 +1,4 @@
 <<<
-//[#insns-load-16bit-sprel,reftext="Load (C.CLWSP, C.CLDSP, C.LWSP, C.LDSP), 16-bit encodings"]
-
-[#C_CLWSP,reftext="C.CLWSP"]
-==== C.CLWSP
-
-See <<C_LDSP>>.
-
-[#C_CLDSP,reftext="C.CLDSP"]
-==== C.CLDSP
-
-See <<C_LDSP>>.
 
 [#C_LWSP,reftext="C.LWSP"]
 ==== C.LWSP
@@ -22,13 +11,13 @@ See <<C_LDSP>>.
 ==== C.LDSP
 
 Synopsis::
-Load (C.CLWSP, C.CLDSP, C.LWSP, C.LDSP), 16-bit encodings
+Load (C.LWSP, C.LDSP), 16-bit encodings
 
 Capability Mode Mnemonics (RV64)::
-`c.cld/c.clw rd, offset(csp)`
+`c.ld/c.lw rd, offset(csp)`
 
 Capability Mode Expansions (RV64)::
-`cld/clw rd, offset(csp)`
+`ld/lw rd, offset(csp)`
 
 Legacy Mode Mnemonics (RV64)::
 `c.ld/c.lw rd, offset(sp)`
@@ -37,10 +26,10 @@ Legacy Mode Expansions (RV64)::
 `ld/lw rd, offset(sp)`
 
 Capability Mode Mnemonics (RV32)::
-`c.clw rd, offset(csp)`
+`c.lw rd, offset(csp)`
 
 Capability Mode Expansions (RV32)::
-`clw rd, offset(csp)`
+`lw rd, offset(csp)`
 
 Legacy Mode Mnemonics (RV32)::
 `c.lw rd, offset(sp)`
@@ -59,17 +48,13 @@ Standard stack pointer relative load instructions, authorised by the capability
 
 include::load_exceptions.adoc[]
 
-Prerequisites for C.CLDSP::
-RV64, and {c_cheri_base_ext_names}
-
-Prerequisites for C.CLWSP::
-{c_cheri_base_ext_names}
-
 Prerequisites for C.LDSP::
+RV64, and {c_cheri_base_ext_names}, or +
 RV64, and {c_cheri_legacy_ext_names}
 
 Prerequisites for C.LWSP::
+{c_cheri_base_ext_names}, or +
 {c_cheri_legacy_ext_names}
 
 Operation (after expansion to 32-bit encodings)::
- See <<CLW>>, <<CLD>>, <<LW>>, <<LD>>
+ See <<LW>>, <<LD>>