tidy up

src/cheri-pte-ext.adoc

@@ -169,10 +169,10 @@ and the capability read from memory optionally has its tag set^1^.
 ^2^ See <<section_hardware_pte_updates>>.
 
 The exceptions added by {cheri_pte_ext_name} reuse the load page fault and store/AMO page fault exception cause values,
-and so the cause of the exception can be determined by software by checking bit zero of <<mtval2>>,
+and so the cause of the exception can be determined by software by checking the value in <<mtval2>>,
 <<stval2>> etc.
 
-They are prioritized against the standard page fault exceptions as shown in <<exception-priority>>.
+TThe behavior when multiple page fault types are detected at once is shown in <<mtval2-page-fault>>.
 
 [#section_hardware_pte_updates]
 === Enabling Software or Hardware PTE updates

src/riscv-integration.adoc

@@ -739,7 +739,7 @@ CHERI load PTE fault^3^
 
 ^1^ The higher priority CHERI <<cheri_pte_ext,PTE>> page fault covers capability loads or atomics where the loaded tag _is not_ checked, and all capability stores and atomics where the stored tag is set.
 
-^2^ CHERI <<cheri_pte_ext,PTE>> page fault exceptions have the same priority against access faults as normal RISC-V page faults. If a normal RISC-V page fault _and_ a CHERI <<cheri_pte_ext,PTE>> fault are both detected simultaneously, then both are recorded as shown in <<mtval2-page-faults>>
+^2^ CHERI <<cheri_pte_ext,PTE>> page fault exceptions have the same priority against access faults as normal RISC-V page faults. If a normal RISC-V page fault _and_ a CHERI <<cheri_pte_ext,PTE>> fault are both detected simultaneously, then both are recorded as shown in <<mtval2-page-fault>>.
 
 ^3^ The lower priority <<cheri_pte_ext,PTE>> fault only covers capability loads and atomics where the loaded tag _is_ checked.
 
@@ -843,7 +843,7 @@ Page faults can be caused by normal RISC-V page faults and also by CHERI <<cheri
 If both are detected at once, then both are recorded.
 
 .mtval2 for page faults
-[#mtval2-page-faults,width=55%,float="center",align="center",options=header]
+[#mtval2-page-fault,width=70%,float="center",align="center",cols="2,1",options=header]
 |==============================================================================
 | Fault                                                   | Value
 | RISC-V page fault                                       | 0