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Merge pull request #98 from andresag01/fix-issue-50
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Document that DDC/DDDC are address pointers and can be compressed
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@tariqkurd-repo
tariqkurd-repo authored Feb 9, 2024
2 parents 6a94e11 + fe24326 commit 749e4b0
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32 changes: 16 additions & 16 deletions src/csv/CHERI_CSR.csv
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@@ -1,33 +1,33 @@
"Extended CSR","CLEN Address","Alias","XLEN Address","Mode","Permissions","Reset Value","Action on XLEN write","Action on CLEN write","Executable Vector","Unseal On Execution","Store full metadata","Zcheri_legacy","Zcheri_purecap","Prerequisites","Description","","","","","","","","","","","","","","","","","","","","",""
"Extended CSR","CLEN Address","Alias","XLEN Address","Mode","Permissions","Reset Value","Action on XLEN write","Action on CLEN write","Executable Vector","Data Pointer","Unseal On Execution","Store full metadata","Zcheri_legacy","Zcheri_purecap","Prerequisites","Description","","","","","","","","","","","","","","","","","","","","",""
"dpcc","0x7b9","dpc","0x7b1","D","DRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","✔","","✔","✔","Sdext","Debug Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
"dscratch0c","0x7ba","dscratch0","0x7b2","D","DRW, <<asr_perm>>","<<infinite-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","✔","✔","✔","Sdext","Debug Scratch Capability 0","","","","","","","","","","","","","","","","","","","","",""
"dscratch1c","0x7bb","dscratch1","0x7b3","D","DRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","✔","✔","✔","Sdext","Debug Scratch Capability 1","","","","","","","","","","","","","","","","","","","","",""
direct write if address didn't change","✔","","✔","","✔","✔","Sdext","Debug Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
"dscratch0c","0x7ba","dscratch0","0x7b2","D","DRW, <<asr_perm>>","<<infinite-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","Sdext","Debug Scratch Capability 0","","","","","","","","","","","","","","","","","","","","",""
"dscratch1c","0x7bb","dscratch1","0x7b3","D","DRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","Sdext","Debug Scratch Capability 1","","","","","","","","","","","","","","","","","","","","",""
"mtvecc","0x765","mtvec","0x305","M","MRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
Vector range check ^*^ if vectored mode is programmed.","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
Vector range check ^*^ if vectored mode is programmed.","✔","","","✔","✔","M-mode","Machine Trap-Vector Base-Address Capability","","","","","","","","","","","","","","","","","","","","",""
"mscratchc","0x760","mscratch","0x340","M","MRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","✔","✔","✔","M-mode","Machine Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
Vector range check ^*^ if vectored mode is programmed.","✔","","","","✔","✔","M-mode","Machine Trap-Vector Base-Address Capability","","","","","","","","","","","","","","","","","","","","",""
"mscratchc","0x760","mscratch","0x340","M","MRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","M-mode","Machine Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
"mepcc","0x761","mepc","0x341","M","MRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","✔","","✔","✔","M-mode","Machine Exception Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
direct write if address didn't change","✔","","✔","","✔","✔","M-mode","Machine Exception Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
"stvecc","0x505","stvec","0x105","S","SRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
Vector range check ^*^ if vectored mode is programmed.","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
Vector range check ^*^ if vectored mode is programmed.","✔","","","✔","✔","S-mode","Supervisor Trap-Vector Base-Address Capability","","","","","","","","","","","","","","","","","","","","",""
"sscratchc","0x540","sscratch","0x140","S","SRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","✔","✔","✔","S-mode","Supervisor Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
Vector range check ^*^ if vectored mode is programmed.","✔","","","","✔","✔","S-mode","Supervisor Trap-Vector Base-Address Capability","","","","","","","","","","","","","","","","","","","","",""
"sscratchc","0x540","sscratch","0x140","S","SRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","S-mode","Supervisor Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
"sepcc","0x541","sepc","0x141","S","SRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","✔","","✔","✔","S-mode","Supervisor Exception Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
direct write if address didn't change","✔","","✔","","✔","✔","S-mode","Supervisor Exception Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
"jvtc","0x417","jvt","0x017","U","URW","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","","","✔","✔","Zcmt","Jump Vector Table Capability","","","","","","","","","","","","","","","","","","","","",""
"dddc","0x7bc","","","D","DRW, <<asr_perm>>","<<null-cap>>","","","","","","✔","","Sdext","Debug Default Data Capabilty (saved/restored on debug mode entry/exit)","","","","","","","","","","","","","","","","","","","","",""
"mtdc","0x74c","","","M","MRW, <<asr_perm>>","<<null-cap>>","","","","","","✔","","M-mode","Machine Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"stdc","0x163","","","S","SRW, <<asr_perm>>","<<null-cap>>","","","","","","✔","","S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"ddc","0x416","","","U","URW","<<infinite-cap>>","","","","","","✔","","none","User Default Data Capability","","","","","","","","","","","","","","","","","","","","",""
direct write if address didn't change","✔","","","","✔","✔","Zcmt","Jump Vector Table Capability","","","","","","","","","","","","","","","","","","","","",""
"dddc","0x7bc","","","D","DRW, <<asr_perm>>","<<null-cap>>","","","","✔","","","✔","","Sdext","Debug Default Data Capabilty (saved/restored on debug mode entry/exit)","","","","","","","","","","","","","","","","","","","","",""
"mtdc","0x74c","","","M","MRW, <<asr_perm>>","<<null-cap>>","","","","","","","✔","","M-mode","Machine Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"stdc","0x163","","","S","SRW, <<asr_perm>>","<<null-cap>>","","","","","","","✔","","S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"ddc","0x416","","","U","URW","<<infinite-cap>>","","","","✔","","","✔","","none","User Default Data Capability","","","","","","","","","","","","","","","","","","","","",""
"pcc","0xcb0","","","U","URO","<<infinite-cap>>
(address = boot address)","","","✔","","","✔","✔","none","User Program Counter Capability (to allow reading in legacy mode)","","","","","","","","","","","","","","","","","","","","",""
(address = boot address)","","","✔","","","","✔","✔","none","User Program Counter Capability (to allow reading in legacy mode)","","","","","","","","","","","","","","","","","","","","",""
6 changes: 6 additions & 0 deletions src/riscv-legacy-integration.adoc
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Expand Up @@ -241,6 +241,9 @@ When debug mode is exited by executing <<DRET>>, the hart's <<ddc>> is updated t
the capability stored in <<dddc>>. A debugger may write <<dddc>> to change the
hart's context.

As shown in xref:CSR_exevectors[xrefstyle=short], <<dddc>> is a data pointer,
so it does not need to be able to hold all possible invalid addresses.

[#section_cheri_disable]
=== Disabling CHERI Features

Expand Down Expand Up @@ -378,5 +381,8 @@ operand to authorise all data memory accesses when the current CHERI mode is
Legacy. This register must be readable in any implementation. Its reset value
is the <<infinite-cap>> capability.

As shown in xref:CSR_exevectors[xrefstyle=short], <<ddc>> is a data pointer,
so it does not need to be able to hold all possible invalid addresses.

.Unprivileged default data capability register
include::img/ddcreg.edn[]
6 changes: 4 additions & 2 deletions src/scripts/generate_tables.py
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Expand Up @@ -685,7 +685,7 @@ def check(self,row):
return row[self.header.index("Extended CSR")] != ""

class csr_exevectors(table):
cols = ["Extended CSR", "Executable Vector", "Unseal On Execution"]
cols = ["Extended CSR", "Executable Vector", "Data Pointer", "Unseal On Execution"]
indices = []

def __init__(self, filename, header):
Expand All @@ -707,7 +707,9 @@ def update(self, row):
self.file.write(outStr+'\n')

def check(self,row):
return row[self.header.index("Executable Vector")] == "✔" or row[self.header.index("Unseal On Execution")] == "✔"
return row[self.header.index("Executable Vector")] == "✔" or \
row[self.header.index("Unseal On Execution")] == "✔" or \
row[self.header.index("Data Pointer")] == "✔"

class csr_metadata(table):
cols = ["Extended CSR", "Store full metadata"]
Expand Down
4 changes: 2 additions & 2 deletions src/tables.adoc
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Expand Up @@ -108,9 +108,9 @@ NOTE: Implementations which allow misa.C to be writable need to legalise *Xepcc*
NOTE: <<CSRRW>> make an XLEN-wide access to the XLEN-wide CSR aliases or a CLEN-wide access to the CLEN-wide aliases for all extended CSRs.
{non-csrrw-and} only make XLEN-wide accesses even if the CLEN-wide alias is specified.

.CLEN-wide CSRs storing executable vectors
.CLEN-wide CSRs storing executable vectors or data pointers
[#CSR_exevectors]
[width="100%",options=header,cols="1,1,1"]
[width="100%",options=header,cols="1,1,1,1"]
|==============================================================================
include::generated/csr_exevectors_table_body.adoc[]
|==============================================================================
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