Add links to the Invalid address conversion section

Since this section only appears much later in the document, add a
forward reference to help readers.

Co-authored-by: Lawrence Esswood <[email protected]>

src/hypervisor-integration.adoc

@@ -131,7 +131,7 @@ The <<vsepcc>> register is a renamed extension of <<vsepc>> that is able to
 hold a capability. Its reset value is the <<infinite-cap>> capability.
 
 As shown in xref:CSR_exevectors[xrefstyle=short], <<vsepcc>> is an executable
-vector, so it need not be able to hold all possible invalid addresses.
+vector, so it need not be able to hold all possible invalid addresses (see <<section_invalid_addr_conv>>).
 Additionally, the capability in <<vsepcc>> is unsealed when it is installed in
 <<pcc>> on execute of an <<SRET>> instruction. The handling of <<vsepcc>> is
 otherwise identical to <<mepcc>>, but in virtual supervisor mode.

src/riscv-hybrid-integration.adoc

@@ -317,7 +317,7 @@ the capability stored in <<dddc>>. A debugger may write <<dddc>> to change the
 hart's context.
 
 As shown in xref:CSR_exevectors[xrefstyle=short], <<dddc>> is a data pointer,
-so it does not need to be able to hold all possible invalid addresses.
+so it does not need to be able to hold all possible invalid addresses (see <<section_invalid_addr_conv>>).
 
 [#section_cheri_disable]
 === Disabling CHERI Registers and Instructions
@@ -533,7 +533,7 @@ NOTE: CRE is not required for the implicit access required by checking memory ac
 {REQUIRE_HYBRID_CSR}
 
 As shown in xref:CSR_exevectors[xrefstyle=short], <<ddc>> is a data pointer,
-so it does not need to be able to hold all possible invalid addresses.
+so it does not need to be able to hold all possible invalid addresses (see <<section_invalid_addr_conv>>).
 
 .Unprivileged default data capability register
 include::img/ddcreg.edn[]

src/riscv-integration.adoc

@@ -99,7 +99,7 @@ instructions, such as <<AUIPC>> or <<JAL>>, in debug mode.
 include::img/pccreg.edn[]
 
 <<pcc>> is an executable
-vector, so it need not be able to hold all possible invalid addresses.
+vector, so it need not be able to hold all possible invalid addresses (see <<section_invalid_addr_conv>>).
 
 [#section_cap_instructions]
 === Capability Instructions
@@ -570,7 +570,7 @@ encountered an exception. Otherwise, <<mepcc>> is never written by the
 implementation, though it may be explicitly written by software.
 
 As shown in xref:CSR_exevectors[xrefstyle=short], <<mepcc>> is an executable
-vector, so it does not need to be able to hold all possible invalid addresses.
+vector, so it does not need to be able to hold all possible invalid addresses (see <<section_invalid_addr_conv>>).
 Additionally, the capability in <<mepcc>> is unsealed when it is installed in
 <<pcc>> on execution of an <<MRET>> instruction.
 
@@ -939,7 +939,7 @@ The <<sepcc>> register is a renamed extension of <<sepc>> that is able to hold a
 capability. Its reset value is the <<infinite-cap>> capability.
 
 As shown in xref:CSR_exevectors[xrefstyle=short], <<sepcc>> is an executable
-vector, so it need not be able to hold all possible invalid addresses.
+vector, so it need not be able to hold all possible invalid addresses (see <<section_invalid_addr_conv>>).
 Additionally, the capability in <<sepcc>> is unsealed when it is installed in
 <<pcc>> on execution of an <<SRET>> instruction. The handling of <<sepcc>> is
 otherwise identical to <<mepcc>>, but in supervisor mode.