clarify branches and x0/c0

riscv · Jan 31, 2024 · accfc3b · accfc3b
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Showing 2 changed files with 7 additions and 3 deletions.
diff --git a/src/insns/jalr_cap_32bit.adoc b/src/insns/jalr_cap_32bit.adoc
@@ -29,7 +29,9 @@ include::wavedrom/ct-unconditional-jalr-cap.adoc[]
 Capability Mode Description::
 JALR.PCC allows unconditional jumps to a target integer address. The target
 address in `rs1` is installed in the address field of the <<pcc>>. The address
-of the instruction following the jump (<<pcc>> + 4) is written to `rd`. This is identical to the standard <<JALR>> instruction, but with zero offset.
+of the instruction following the jump (<<pcc>> + 4) would be written to `rd`, but
+since this is c0 the result is discarded.
+This is identical to the standard <<JALR>> instruction, but with zero offset.
 
 Legacy Mode Description::
 JALR.CAP allows unconditional jumps to a target capability. The capability in

diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc
@@ -177,7 +177,8 @@ for software to discover and/or control the behaviour#
 The indirect jump and link <<pcc>> (<<JALR_PCC>>) instruction allows unconditional
 jumps to a target address. The target address is provided in an *x* register;
 the new address is installed in the address field of the <<pcc>>. The address of
-the instruction following the jump (*pc* + 4) is written to an *x* register.
+the instruction following the jump (*pc* + 4) is written to an *x* register, unless
+it is x0, which causes the write to be discarded.
 <<JALR_PCC>> causes an exception when a minimum sized instruction at the
 target address is not within the bounds of the <<pcc>> or the target address is
 misaligned.
@@ -223,7 +224,8 @@ The capability jump and link (<<CJAL>>) instruction replaces jump and link (<<JA
 the same encoding. <<CJAL>> sign-extends the offset and adds it to the address of
 the jump instruction to form the target address. The target address is
 installed in the address field of <<pcc>>. The capability with the address of the
-instruction following the jump (<<pcc>> + 4) is written to a *c* register.
+instruction following the jump (<<pcc>> + 4) is written to a *c* register. In
+case of c0, the capability write is discarded.
 
 The capability jump and link register (<<CJALR>>) instruction replaces the jump
 and link register (<<JALR>>) instruction at the same encoding. This instruction