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Fix issue 42 #46

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merged 2 commits into from
Jan 25, 2024
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Fix issue 42 #46

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1e92da3
Fix issue 42
tariqkurd-repo Jan 25, 2024
9520d74
Merge branch 'main' into tariqkurd-repo-patch-1
tariqkurd-repo Jan 25, 2024
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5 changes: 3 additions & 2 deletions src/riscv-legacy-integration.adoc
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Expand Up @@ -189,8 +189,9 @@ When the XLEN-bit alias is used by <<CSRRW>>:
* Only XLEN bits from the *x* source are written to the capability address
field.
** The tag and metadata are updated as specified in <<extended_CSR_writing>>.
* Only XLEN bits are read from the capability address field, which is zero
extended to the destination *x* register.
* Only XLEN bits are read from the capability address field, which are extended
to XLENMAX bits according to cite:[riscv-unpriv-spec] and are then written
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to the destination *x* register.

When the CLEN-bit alias is used by <<CSRRW>>:

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