clarify PTE fault exception priority, and add into instruction pages#485
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tariqkurd-repo merged 9 commits intomainfrom Dec 17, 2024
Merged
clarify PTE fault exception priority, and add into instruction pages#485tariqkurd-repo merged 9 commits intomainfrom
tariqkurd-repo merged 9 commits intomainfrom
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Timmmm
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Dec 13, 2024
Timmmm
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Yeah I think this is unambiguous, and can be implemented easily in Sail, and I can't see any reason why it would be hard to implement in designs. Just one minor typo.
tariqkurd-repo
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Dec 16, 2024
Signed-off-by: Tariq Kurd <tariqandlaura@gmail.com>
Timmmm
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tariqkurd-repo
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Dec 17, 2024
tariqkurd-repo
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Dec 17, 2024
Signed-off-by: Tariq Kurd <tariqandlaura@gmail.com>
jrtc27
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Dec 17, 2024
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| If a store page fault is caused by a CHERI <<cheri_pte_ext,PTE>> fault, then set bit zero of <<mtval2>> to 1 and all other bits to 0, otherwise set all bits to zero. | ||
| NOTE: Reporting both allows the software the choice about which action to take first, for example a write to a |
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This confuses me. Load-side revocation will never do any sweeping on stores, so value 2 isn't useful, it will be treated the same as 1. As for loads, yes, sweeping occurs there, but there's nothing else really to do if both faults occur (for non-tag-dependent implementations) over and above just a CHERI PTE fault, and if your implementation is tag-dependent then the RISC-V page fault and CHERI PTE fault are strictly serial so it's impossible to have both at once.
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Fixes #484