small fixes #530
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small fixes #530
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arichardson
approved these changes
Feb 10, 2025
andresag01
reviewed
Feb 11, 2025
| @@ -26,14 +26,14 @@ privileged architecture specified in the RISC-V ISA. | |||
| === Memory | |||
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| A hart supporting {cheri_base_ext_name} has a single byte-addressable address | |||
| space of 2^XLEN^ bytes for all memory accesses. Each memory region capable of | |||
| space of 2^MXLEN^ bytes for all memory accesses. Each memory region capable of | |||
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@tariqkurd-repo @arichardson : This was correct and it was taken directly from the RISC-V unprivileged specification where it says (see Page 16 Section 1.4 here):
A RISC-V hart has a single byte-addressable address space of 2^XLEN^ bytes for all memory accesses.
It is meant to be the effective XLEN of the machine which can be MXLEN or SXLEN or UXLEN depending CSRs. The idea is that the byte-addressable memory space is just like in CHERI-less RISC-V so we are fully compatible, but capability bounds remain encoded in MXLEN width regardless of the effective XLEN.
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