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Revert MXLEN to XLEN in RV memory description #532

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Revert MXLEN to XLEN in RV memory description #532

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4 changes: 2 additions & 2 deletions src/riscv-integration.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -26,14 +26,14 @@ privileged architecture specified in the RISC-V ISA.
=== Memory

A hart supporting {cheri_base_ext_name} has a single byte-addressable address
space of 2^MXLEN^ bytes for all memory accesses. Each memory region capable of
space of 2^XLEN^ bytes for all memory accesses. Each memory region capable of
holding a capability also stores a tag bit for each naturally aligned CLEN bits
(e.g. 16 bytes in RV64), so that capabilities with their tag set can only be
stored in naturally aligned addresses. Tags must be atomically bound to the
data they protect.

The memory address space is circular, so the byte at address
2^MXLEN^ - 1 is adjacent to the byte at address zero. A capability's
2^XLEN^ - 1 is adjacent to the byte at address zero. A capability's
<<section_cap_representable_check>> described in xref:section_cap_encoding[xrefstyle=short] is
also circular, so address 0 is within the <<section_cap_representable_check>> of a capability
where address 2^MXLEN^ - 1 is within the bounds.
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