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Smidctrl: Removing eithreshold and eidelivery CSRs #669
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@@ -323,33 +323,20 @@ This approach has several advantages: | |
| This is achieved by reusing the allocated indirect CSR space for the interrupt pending and enable bits in an IMSIC. | ||
| Additional indirect CSR access is provided to the remaining state. | ||
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| ==== Interrupt control interface based on IMSIC | ||
| ==== Interrupt control interface based on IMSIC interface | ||
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| ACLIC provides access to interrupt pending and enable bits of the hart-local APLIC domains using these same mechanisms as access to interrupt pending and enable bits in the interrupt files of an IMSIC. | ||
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| The AIA {eidelivery} CSR defined for the Incoming Message Signaled Interrupt Controller (IMSIC) is extended to provide for an ACLIC delivery mode. | ||
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| [%autowidth,float="center",align="center",cols=">,<",grid=none,frame=none] | ||
| |=== | ||
| |0 = | Interrupt delivery is disabled | ||
| |1 = | Interrupt delivery from the interrupt file is enabled | ||
| |0x20000000 = | Interrupt delivery from an ACLIC (new) | ||
| |0x40000000 = | Interrupt delivery from a PLIC or APLIC is enabled | ||
| |=== | ||
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| If Smidctrl or Ssidctrl extensions are present, {eidelivery} is fixed to 0x20000000. | ||
| The AIA {eidelivery} and {eithreshold} CSRs defined for the Incoming Message Signaled Interrupt Controller (IMSIC) are not included in the scope of Smidctrl/Ssidctrl. | ||
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| NOTE: It is not anticipated that ACLIC implementations would allow dynamically switching eidelivery into other modes. | ||
| If e.g. MSI delivery is required in a system, it is recommended to use the full AIA implementation with IMSIC. | ||
| Therefore, no dynamic selection of ACLIC operation via eidelivery is provided. | ||
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| When interrupts are delivered from an ACLIC, the following behavior is valid: | ||
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| The IMSIC registers {eipk} and {eiek} serve the same functionality as with {eidelivery} = 1, | ||
| In an ACLIC, registers {eipk} and {eiek} serve the same functionality as with {eidelivery} = 1 in an IMSIC, | ||
| i.e. they are the pending and enable bits for an interrupt source `k`. | ||
| The `eip` and `eie` arrays act as an alias of the pending and enable bits of the connected APLIC domain. | ||
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| The {eithreshold} CSR subsumes the functionality of the {ithreshold} register in the APLIC. | ||
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| [NOTE] | ||
| ==== | ||
| Providing access to APLIC pending and enable bits at the hart-level has several advantages over using using an IMSIC with interrupt delivery from an APLIC | ||
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@@ -361,7 +348,7 @@ Providing access to APLIC pending and enable bits at the hart-level has several | |
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| The {xtopei} registers work analogous to the IMSIC operation, | ||
| but map to the current highest-priority pending-and-enabled interrupt of the connected APLIC domain. | ||
| In this delivery mode, the {xtopei} CSR reflect both the interrupt identity and the interrupt priority. | ||
| The {xtopei} CSR reflect both the interrupt identity and the interrupt priority. | ||
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| [%autowidth,float="center",align="center",cols=">,<",grid=none,frame=none] | ||
| |=== | ||
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@@ -660,6 +647,15 @@ for an interrupt to be considered enabled at the hart. | |
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| Register {mithreshold} implements exactly IPRIOLEN bits. | ||
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| [NOTE] | ||
| ==== | ||
| In contrast to existing threshold mechanisms in AIA, | ||
| this CSR applies to major and minor interrupt identities. | ||
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Collaborator
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Since eithreshold is not implemented, xithreshold should be included in sxidctrl, after xtopei?
Collaborator
Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I did think about that. I am not aware of a good use case for thresholds without preemption.
Collaborator
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. AIA provides threholds but not preemption, so I hope there is a use-case! But your point about emabling preemption with an IMSIC is valid - the preemption extension should not be tied to a specific interrupt controller. |
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| It is needed in an efficient implementation of synchronization protocols like | ||
| Priority Ceiling Protocol (PCP) that are used with preemptive interrupt schemes. | ||
| ==== | ||
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| ==== New Previous Interrupt Status ({mpistatus}) CSR | ||
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| A new M-mode CSR, {mpistatus}, holds consolidated state of preempted context. | ||
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