feat(V): add operation() for vmv.v.v and vmv.v.x#1764
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adingank-qualcomm wants to merge 14 commits intoriscv:mainfrom
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feat(V): add operation() for vmv.v.v and vmv.v.x#1764adingank-qualcomm wants to merge 14 commits intoriscv:mainfrom
adingank-qualcomm wants to merge 14 commits intoriscv:mainfrom
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Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Adds a Claude skill that generates IDL operation() bodies for RISC-V instructions from their YAML spec files, writing to the spec if the operation() key is empty or to /tmp/<name>.yaml if already populated. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
- model-instruction-from-spec: remove Sail references (being removed from UDB YAML files), add floating-point register access syntax - extract-instructions-from-subsection: soften exclusion list heading, drop "Two-letter" qualifier from register name exclusion rule Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Model the IDL operation() body for the vector integer move instructions: - vmv.v.v: copy vector register vs1 elements into vd - vmv.v.x: broadcast scalar integer register xs1 into all elements of vd Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
## main #1764 +/- ##
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Coverage 72.24% 72.24%
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Files 52 52
Lines 27671 27671
Branches 6009 6009
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Hits 19992 19992
Misses 7679 7679
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Summary
operation()body forvmv.v.v: copies elements from vector registervs1intovdoperation()body forvmv.v.x: broadcasts scalar integer registerxs1into all elements ofvdBoth implementations follow the standard vector loop pattern: read vector state, compute
vlmax, iterate fromvstarttovl, write elements using bit-slice operations, and resetvstartto 0.Test plan
idlcvmv.v.xvstartis reset to 0 after the loop in both instructions🤖 Generated with Claude Code