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feat(V): add operation() for vmv.v.v and vmv.v.x#1764

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adingank-qualcomm wants to merge 14 commits intoriscv:mainfrom
adingank-qualcomm:ajit/vector-integer-move
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feat(V): add operation() for vmv.v.v and vmv.v.x#1764
adingank-qualcomm wants to merge 14 commits intoriscv:mainfrom
adingank-qualcomm:ajit/vector-integer-move

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Summary

  • Add IDL operation() body for vmv.v.v: copies elements from vector register vs1 into vd
  • Add IDL operation() body for vmv.v.x: broadcasts scalar integer register xs1 into all elements of vd

Both implementations follow the standard vector loop pattern: read vector state, compute vlmax, iterate from vstart to vl, write elements using bit-slice operations, and reset vstart to 0.

Test plan

  • Verify generated IDL compiles with idlc
  • Check element loop bounds match spec (vstart to vl)
  • Confirm scalar truncation to SEW bits in vmv.v.x
  • Confirm vstart is reset to 0 after the loop in both instructions

🤖 Generated with Claude Code

adingank-qualcomm and others added 12 commits March 16, 2026 14:06
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Adds a Claude skill that generates IDL operation() bodies for RISC-V
instructions from their YAML spec files, writing to the spec if the
operation() key is empty or to /tmp/<name>.yaml if already populated.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
- model-instruction-from-spec: remove Sail references (being removed
  from UDB YAML files), add floating-point register access syntax
- extract-instructions-from-subsection: soften exclusion list heading,
  drop "Two-letter" qualifier from register name exclusion rule

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Model the IDL operation() body for the vector integer move instructions:
- vmv.v.v: copy vector register vs1 elements into vd
- vmv.v.x: broadcast scalar integer register xs1 into all elements of vd

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@adingank-qualcomm adingank-qualcomm marked this pull request as draft March 30, 2026 20:39
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codecov Bot commented Apr 29, 2026

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 72.24%. Comparing base (a1225d7) to head (351da05).
⚠️ Report is 1 commits behind head on main.

Additional details and impacted files
@@           Coverage Diff           @@
##             main    #1764   +/-   ##
=======================================
  Coverage   72.24%   72.24%           
=======================================
  Files          52       52           
  Lines       27671    27671           
  Branches     6009     6009           
=======================================
  Hits        19992    19992           
  Misses       7679     7679           
Flag Coverage Δ
idlc 76.18% <ø> (ø)
udb 66.26% <ø> (ø)

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